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nir/algebraic: Mask with shifted constant instead of shift-then-mask

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shader-db:

All Intel platforms had similar results. (Lunar Lake shown)
total instructions in shared programs: 17088766 -> 17088765 (<.01%)
instructions in affected programs: 1375 -> 1374 (-0.07%)
helped: 1 / HURT: 1

total cycles in shared programs: 887873068 -> 887871748 (<.01%)
cycles in affected programs: 136402 -> 135082 (-0.97%)
helped: 2 / HURT: 0

fossil-db:

Lunar Lake
Totals:
Instrs: 924954240 -> 924939317 (-0.00%); split: -0.00%, +0.00%
Subgroup size: 40937696 -> 40937728 (+0.00%)
Cycle count: 106116946509 -> 106116637903 (-0.00%); split: -0.00%, +0.00%
Spill count: 3423930 -> 3423250 (-0.02%); split: -0.02%, +0.00%
Fill count: 4876960 -> 4876045 (-0.02%); split: -0.03%, +0.01%
Max live registers: 193882457 -> 193881816 (-0.00%); split: -0.00%, +0.00%
Max dispatch width: 49078640 -> 49078656 (+0.00%)
Non SSA regs after NIR: 231314214 -> 231314219 (+0.00%); split: -0.00%, +0.00%

Totals from 13809 (0.68% of 2019450) affected shaders:
Instrs: 25433084 -> 25418161 (-0.06%); split: -0.08%, +0.02%
Subgroup size: 32 -> 64 (+100.00%)
Cycle count: 1483550606 -> 1483242000 (-0.02%); split: -0.27%, +0.25%
Spill count: 41466 -> 40786 (-1.64%); split: -1.88%, +0.24%
Fill count: 74195 -> 73280 (-1.23%); split: -2.12%, +0.88%
Max live registers: 2326365 -> 2325724 (-0.03%); split: -0.05%, +0.02%
Max dispatch width: 234848 -> 234864 (+0.01%)
Non SSA regs after NIR: 3394104 -> 3394109 (+0.00%); split: -0.00%, +0.00%

Meteor Lake and DG2 had similar results. (Meteor Lake shown)
Totals:
Instrs: 997527742 -> 997524495 (-0.00%); split: -0.00%, +0.00%
Subgroup size: 27452928 -> 27452944 (+0.00%)
Cycle count: 93646717070 -> 93649738060 (+0.00%); split: -0.00%, +0.01%
Spill count: 3710125 -> 3709784 (-0.01%); split: -0.03%, +0.02%
Fill count: 5032819 -> 5033191 (+0.01%); split: -0.04%, +0.05%
Max live registers: 121648838 -> 121648528 (-0.00%); split: -0.00%, +0.00%
Max dispatch width: 37811544 -> 37811584 (+0.00%)
Non SSA regs after NIR: 255562054 -> 255565914 (+0.00%); split: -0.00%, +0.00%

Totals from 14438 (0.63% of 2281134) affected shaders:
Instrs: 25974222 -> 25970975 (-0.01%); split: -0.08%, +0.06%
Subgroup size: 16 -> 32 (+100.00%)
Cycle count: 1149710820 -> 1152731810 (+0.26%); split: -0.29%, +0.55%
Spill count: 44445 -> 44104 (-0.77%); split: -2.23%, +1.46%
Fill count: 76172 -> 76544 (+0.49%); split: -2.89%, +3.37%
Max live registers: 1237997 -> 1237687 (-0.03%); split: -0.04%, +0.02%
Max dispatch width: 123528 -> 123568 (+0.03%)
Non SSA regs after NIR: 3490757 -> 3494617 (+0.11%); split: -0.03%, +0.14%

Tiger Lake, Ice Lake, and Skylake had similar results. (Tiger Lake shown)
Totals:
Instrs: 1013364485 -> 1013342384 (-0.00%); split: -0.00%, +0.00%
Cycle count: 85509342602 -> 85500105656 (-0.01%); split: -0.02%, +0.01%
Spill count: 3903944 -> 3903350 (-0.02%); split: -0.02%, +0.01%
Fill count: 6801948 -> 6799368 (-0.04%); split: -0.05%, +0.01%
Max live registers: 122212165 -> 122211859 (-0.00%); split: -0.00%, +0.00%
Max dispatch width: 37805336 -> 37805472 (+0.00%)
Non SSA regs after NIR: 244624956 -> 244628603 (+0.00%); split: -0.00%, +0.00%

Totals from 14835 (0.65% of 2278397) affected shaders:
Instrs: 27522570 -> 27500469 (-0.08%); split: -0.10%, +0.02%
Cycle count: 1128820972 -> 1119584026 (-0.82%); split: -1.53%, +0.71%
Spill count: 46408 -> 45814 (-1.28%); split: -2.04%, +0.76%
Fill count: 99071 -> 96491 (-2.60%); split: -3.14%, +0.54%
Max live registers: 1287967 -> 1287661 (-0.02%); split: -0.04%, +0.02%
Max dispatch width: 126600 -> 126736 (+0.11%)
Non SSA regs after NIR: 3438628 -> 3442275 (+0.11%); split: -0.03%, +0.14%

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38979>
This commit is contained in:
Ian Romanick 2025-12-11 13:03:11 -08:00 • committed by Marge Bot
parent 2418c91537
commit 66fd4d72fd
1 changed files with 5 additions and 0 deletions
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5
src/compiler/nir/nir_opt_algebraic.py
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@ -2580,6 +2580,11 @@ optimizations.extend([
(('ine', ('ubfe(is_used_once)', a, '#b', '#c'), 0), ('ine', ('iand', a, ('ishl', ('ushr', 0xffffffff, ('ineg', c)), b)), 0)),
(('ieq', ('ubfe(is_used_once)', a, '#b', '#c'), 0), ('ieq', ('iand', a, ('ishl', ('ushr', 0xffffffff, ('ineg', c)), b)), 0)),
(('ine', ('iand(is_used_once)', ('ushr', a, '#b'), '#c'), 0), ('ine', ('iand', a, ('ishl', c, b)), 0)),
(('ine', ('iand(is_used_once)', ('ishl', a, '#b'), '#c'), 0), ('ine', ('iand', a, ('ushr', c, b)), 0)),
(('ieq', ('iand(is_used_once)', ('ushr', a, '#b'), '#c'), 0), ('ieq', ('iand', a, ('ishl', c, b)), 0)),
(('ieq', ('iand(is_used_once)', ('ishl', a, '#b'), '#c'), 0), ('ieq', ('iand', a, ('ushr', c, b)), 0)),
(('ifind_msb', 'value'),
('ufind_msb', ('bcsel', ('ilt', 'value', 0), ('inot', 'value'), 'value')),
'options->lower_ifind_msb && !options->has_find_msb_rev && !options->has_uclz'),