From 66dd70adc556fdb3ee2c00d719e0bd94af869cdf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Wed, 25 Dec 2024 12:44:59 -0500 Subject: [PATCH] amd: lower load_gs_wave_id_amd in NIR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reviewed-by: Timur Kristóf Part-of: --- src/amd/common/ac_nir.c | 8 ++++++++ src/amd/compiler/aco_instruction_selection.cpp | 12 ------------ src/amd/llvm/ac_nir_to_llvm.c | 9 --------- 3 files changed, 8 insertions(+), 21 deletions(-) diff --git a/src/amd/common/ac_nir.c b/src/amd/common/ac_nir.c index b5daf6dac95..2ad58c38d71 100644 --- a/src/amd/common/ac_nir.c +++ b/src/amd/common/ac_nir.c @@ -324,6 +324,14 @@ lower_intrinsic_to_arg(nir_builder *b, nir_instr *instr, void *state) replacement = nir_vec2(b, offset_i, offset_j); break; } + case nir_intrinsic_load_gs_wave_id_amd: + if (s->args->merged_wave_info.used) + replacement = ac_nir_unpack_arg(b, s->args, s->args->merged_wave_info, 16, 8); + else if (s->args->gs_wave_id.used) + replacement = ac_nir_load_arg(b, s->args, s->args->gs_wave_id); + else + unreachable("Shader doesn't have GS wave ID."); + break; default: return false; } diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 44740b4d617..343cd375638 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -8896,18 +8896,6 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) bld.sopp(aco_opcode::s_sendmsg, bld.m0(m0_content), imm); break; } - case nir_intrinsic_load_gs_wave_id_amd: { - Temp dst = get_ssa_temp(ctx, &instr->def); - if (ctx->args->merged_wave_info.used) - bld.pseudo(aco_opcode::p_extract, Definition(dst), bld.def(s1, scc), - get_arg(ctx, ctx->args->merged_wave_info), Operand::c32(2u), Operand::c32(8u), - Operand::zero()); - else if (ctx->args->gs_wave_id.used) - bld.copy(Definition(dst), get_arg(ctx, ctx->args->gs_wave_id)); - else - unreachable("Shader doesn't have GS wave ID."); - break; - } case nir_intrinsic_is_subgroup_invocation_lt_amd: { Temp src = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa)); unsigned offset = nir_intrinsic_base(instr); diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index b4ff9afcd65..dc0fe4032b6 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -2989,15 +2989,6 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins ac_build_sendmsg(&ctx->ac, imm, m0_content); break; } - case nir_intrinsic_load_gs_wave_id_amd: { - if (ctx->args->merged_wave_info.used) - result = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 16, 8); - else if (ctx->args->gs_wave_id.used) - result = ac_get_arg(&ctx->ac, ctx->args->gs_wave_id); - else - unreachable("Shader doesn't have GS wave ID."); - break; - } case nir_intrinsic_load_tess_coord: { LLVMValueRef coord[] = { ctx->abi->tes_u_replaced ? ctx->abi->tes_u_replaced : ac_get_arg(&ctx->ac, ctx->args->tes_u),