mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-06 02:58:05 +02:00
r600: rework DB render setup
- consolidate DB render setup - only enable perfect ZPASS counts and cull disable when OQ is active - enable early Z
This commit is contained in:
parent
37676b396a
commit
66d6f9e860
4 changed files with 73 additions and 42 deletions
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@ -393,26 +393,6 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
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SETfield(r700->ps.SQ_PGM_EXPORTS_PS.u32All, fp->r700Shader.exportMode,
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EXPORT_MODE_shift, EXPORT_MODE_mask);
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R600_STATECHANGE(context, db);
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if(fp->r700Shader.killIsUsed)
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{
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SETbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
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}
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else
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{
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CLEARbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
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}
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if(fp->r700Shader.depthIsExported)
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{
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SETbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
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}
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else
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{
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CLEARbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
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}
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// emit ps input map
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unBit = 1 << FRAG_ATTRIB_WPOS;
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if(mesa_fp->Base.InputsRead & unBit)
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@ -479,9 +459,12 @@ GLboolean r700SetupFragmentProgram(GLcontext * ctx)
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}
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}
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R600_STATECHANGE(context, cb);
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exportCount = (r700->ps.SQ_PGM_EXPORTS_PS.u32All & EXPORT_MODE_mask) / (1 << EXPORT_MODE_shift);
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r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1;
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if (r700->CB_SHADER_CONTROL.u32All != ((1 << exportCount) - 1))
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{
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R600_STATECHANGE(context, cb);
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r700->CB_SHADER_CONTROL.u32All = (1 << exportCount) - 1;
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}
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/* sent out shader constants. */
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paramList = fp->mesa_program.Base.Parameters;
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@ -59,9 +59,7 @@
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void r700WaitForIdle(context_t *context);
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void r700WaitForIdleClean(context_t *context);
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GLboolean r700SendTextureState(context_t *context);
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static unsigned int r700PrimitiveType(int prim);
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void r600UpdateTextureState(GLcontext * ctx);
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GLboolean r700SyncSurf(context_t *context,
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struct radeon_bo *pbo,
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uint32_t read_domain,
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@ -891,7 +889,7 @@ static GLboolean r700TryDrawPrims(GLcontext *ctx,
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r700SetScissor(context);
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r700SetupVertexProgram(ctx);
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r700SetupFragmentProgram(ctx);
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r600UpdateTextureState(ctx);
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r700UpdateShaderStates(ctx);
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GLuint emit_end = r700PredictRenderSize(ctx, prim, ib, nr_prims)
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+ context->radeon.cmdbuf.cs->cdw;
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@ -54,7 +54,7 @@
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#include "r700_fragprog.h"
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#include "r700_vertprog.h"
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void r600UpdateTextureState(GLcontext * ctx);
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static void r700SetClipPlaneState(GLcontext * ctx, GLenum cap, GLboolean state);
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static void r700UpdatePolygonMode(GLcontext * ctx);
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static void r700SetPolygonOffsetState(GLcontext * ctx, GLboolean state);
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@ -191,6 +191,70 @@ static void r700InvalidateState(GLcontext * ctx, GLuint new_state) //-----------
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context->radeon.NewGLState |= new_state;
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}
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static void r700SetDBRenderState(GLcontext * ctx)
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{
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context_t *context = R700_CONTEXT(ctx);
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R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
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struct r700_fragment_program *fp = (struct r700_fragment_program *)
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(ctx->FragmentProgram._Current);
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R600_STATECHANGE(context, db);
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SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
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SETfield(r700->DB_SHADER_CONTROL.u32All, EARLY_Z_THEN_LATE_Z, Z_ORDER_shift, Z_ORDER_mask);
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/* XXX not sure if this is required */
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if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
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SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
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/* XXX need to enable htile for hiz/s */
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SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
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SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
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SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
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if (context->radeon.query.current)
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{
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SETbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
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if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
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{
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SETbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit);
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}
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}
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else
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{
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CLEARbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
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if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
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{
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CLEARbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit);
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}
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}
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if (fp)
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{
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if (fp->r700Shader.killIsUsed)
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{
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SETbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
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}
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else
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{
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CLEARbit(r700->DB_SHADER_CONTROL.u32All, KILL_ENABLE_bit);
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}
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if (fp->r700Shader.depthIsExported)
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{
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SETbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
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}
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else
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{
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CLEARbit(r700->DB_SHADER_CONTROL.u32All, Z_EXPORT_ENABLE_bit);
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}
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}
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}
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void r700UpdateShaderStates(GLcontext * ctx)
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{
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r700SetDBRenderState(ctx);
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r600UpdateTextureState(ctx);
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}
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static void r700SetDepthState(GLcontext * ctx)
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{
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context_t *context = R700_CONTEXT(ctx);
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@ -1672,24 +1736,10 @@ void r700InitState(GLcontext * ctx) //-------------------
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r700Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test);
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r700DepthMask(ctx, ctx->Depth.Mask);
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r700DepthFunc(ctx, ctx->Depth.Func);
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SETbit(r700->DB_SHADER_CONTROL.u32All, DUAL_EXPORT_ENABLE_bit);
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r700->DB_DEPTH_CLEAR.u32All = 0x3F800000;
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r700->DB_RENDER_CONTROL.u32All = 0;
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SETbit(r700->DB_RENDER_CONTROL.u32All, STENCIL_COMPRESS_DISABLE_bit);
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SETbit(r700->DB_RENDER_CONTROL.u32All, DEPTH_COMPRESS_DISABLE_bit);
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r700->DB_RENDER_OVERRIDE.u32All = 0;
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if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
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SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
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SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
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SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
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SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
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SETbit(r700->DB_RENDER_OVERRIDE.u32All, NOOP_CULL_DISABLE_bit);
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if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
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{
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CLEARbit(r700->DB_RENDER_CONTROL.u32All, PERFECT_ZPASS_COUNTS_bit);
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}
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r700SetDBRenderState(ctx);
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r700->DB_ALPHA_TO_MASK.u32All = 0;
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SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
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@ -35,7 +35,7 @@
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extern void r700UpdateStateParameters(GLcontext * ctx, GLuint new_state);
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extern void r700UpdateShaders (GLcontext * ctx);
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extern void r700UpdateShaders2(GLcontext * ctx);
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extern void r700UpdateShaderStates(GLcontext * ctx);
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extern void r700UpdateViewportOffset(GLcontext * ctx);
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