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pan/compiler: Split lower_varyings_io into fs_inputs and vs_outputs
Signed-off-by: Lorenzo Rossi <lorenzo.rossi@collabora.com> Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40537>
This commit is contained in:
Lorenzo Rossi
Marge Bot
parent
b1acc1aa89
commit
66bee415ad
3 changed files with 123 additions and 112 deletions
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@ -8,6 +8,7 @@ libpanfrost_compiler_files = files(
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'pan_nir_lower_bool_to_bitsize.c',
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'pan_nir_lower_frag_coord_zw.c',
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'pan_nir_lower_framebuffer.c',
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'pan_nir_lower_fs_inputs.c',
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'pan_nir_lower_fs_outputs.c',
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'pan_nir_lower_helper_invocation.c',
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'pan_nir_lower_image_index.c',
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@ -16,8 +17,8 @@ libpanfrost_compiler_files = files(
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'pan_nir_lower_sample_position.c',
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'pan_nir_lower_store_component.c',
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'pan_nir_lower_texel_buffer_index.c',
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'pan_nir_lower_varyings_io.c',
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'pan_nir_lower_vertex_id.c',
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'pan_nir_lower_vs_outputs.c',
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'pan_nir_lower_xfb.c',
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'pan_nir_resize_varying_io.c',
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)
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121
src/panfrost/compiler/pan_nir_lower_fs_inputs.c
Normal file
121
src/panfrost/compiler/pan_nir_lower_fs_inputs.c
Normal file
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@ -0,0 +1,121 @@
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/*
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* Copyright (C) 2025 Collabora, Ltd.
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* SPDX-License-Identifier: MIT
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*/
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#include "pan_nir.h"
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#include "nir_builder.h"
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#include "panfrost/model/pan_model.h"
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struct lower_fs_inputs_ctx {
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unsigned arch;
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const struct pan_varying_layout *varying_layout;
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struct pan_shader_info *info;
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};
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static bool
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lower_fs_input_load(struct nir_builder *b,
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nir_intrinsic_instr *load, void *cb_data)
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{
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const struct lower_fs_inputs_ctx *ctx = cb_data;
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if (load->intrinsic != nir_intrinsic_load_input &&
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load->intrinsic != nir_intrinsic_load_interpolated_input)
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return false;
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const nir_io_semantics sem = nir_intrinsic_io_semantics(load);
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const nir_alu_type dest_type = nir_intrinsic_dest_type(load);
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/* Indirect array varyings are not yet supported (num_slots > 1) */
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assert(sem.num_slots == 1);
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assert(nir_src_as_uint(*nir_get_io_offset_src(load)) == 0);
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nir_intrinsic_instr *bary;
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switch (load->intrinsic) {
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case nir_intrinsic_load_input:
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bary = NULL;
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break;
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case nir_intrinsic_load_interpolated_input:
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/* Cannot interpolate ints */
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assert(nir_alu_type_get_base_type(dest_type) == nir_type_float);
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bary = nir_src_as_intrinsic(load->src[0]);
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break;
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default:
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UNREACHABLE("Already handled");
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}
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b->cursor = nir_before_instr(&load->instr);
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const unsigned component = nir_intrinsic_component(load);
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const unsigned load_comps = load->num_components + component;
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const struct pan_varying_slot *slot = NULL;
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bool use_ld_var_buf = false;
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if (ctx->varying_layout && ctx->arch >= 9) {
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pan_varying_layout_require_layout(ctx->varying_layout);
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slot = pan_varying_layout_find_slot(ctx->varying_layout, sem.location);
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assert(slot);
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use_ld_var_buf = slot->offset < pan_ld_var_buf_off_size(ctx->arch);
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}
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nir_def *res;
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if (use_ld_var_buf) {
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const nir_alu_type src_type = slot->alu_type;
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nir_def *offset_B = nir_imm_int(b, slot->offset);
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if (load->intrinsic == nir_intrinsic_load_interpolated_input) {
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res = nir_load_var_buf_pan(b, load_comps, load->def.bit_size,
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offset_B, &bary->def,
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.src_type = src_type,
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.io_semantics = sem);
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} else {
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res = nir_load_var_buf_flat_pan(b, load_comps, load->def.bit_size,
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offset_B,
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.src_type = src_type,
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.io_semantics = sem);
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}
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} else {
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ctx->info->bifrost.uses_ld_var = true;
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const uint32_t base = nir_intrinsic_base(load);
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nir_def *idx = nir_imm_int(b, base);
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if (load->intrinsic == nir_intrinsic_load_interpolated_input) {
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res = nir_load_var_pan(b, load_comps, load->def.bit_size,
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idx, &bary->def,
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.dest_type = dest_type,
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.io_semantics = sem);
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} else {
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res = nir_load_var_flat_pan(b, load_comps, load->def.bit_size, idx,
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.dest_type = dest_type,
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.io_semantics = sem);
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}
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}
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if (component > 0) {
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unsigned swiz[NIR_MAX_VEC_COMPONENTS] = {0, };
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for (unsigned c = 0; c < load->num_components; c++)
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swiz[c] = component + c;
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res = nir_swizzle(b, res, swiz, load->num_components);
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}
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nir_def_replace(&load->def, res);
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return true;
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}
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bool
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pan_nir_lower_fs_inputs(nir_shader *shader, unsigned gpu_id,
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const struct pan_varying_layout *varying_layout,
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struct pan_shader_info *info)
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{
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const struct lower_fs_inputs_ctx ctx = {
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.arch = pan_arch(gpu_id),
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.varying_layout = varying_layout,
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.info = info,
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};
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return nir_shader_intrinsics_pass(shader, lower_fs_input_load,
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nir_metadata_control_flow,
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(void *)&ctx);
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}
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@ -154,114 +154,3 @@ pan_nir_lower_vs_outputs(nir_shader *shader, unsigned gpu_id,
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nir_metadata_control_flow,
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(void *)&ctx);
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}
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struct lower_fs_inputs_ctx {
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unsigned arch;
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const struct pan_varying_layout *varying_layout;
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struct pan_shader_info *info;
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};
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static bool
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lower_fs_input_load(struct nir_builder *b,
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nir_intrinsic_instr *load, void *cb_data)
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{
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const struct lower_fs_inputs_ctx *ctx = cb_data;
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if (load->intrinsic != nir_intrinsic_load_input &&
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load->intrinsic != nir_intrinsic_load_interpolated_input)
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return false;
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const nir_io_semantics sem = nir_intrinsic_io_semantics(load);
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const nir_alu_type dest_type = nir_intrinsic_dest_type(load);
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/* Indirect array varyings are not yet supported (num_slots > 1) */
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assert(sem.num_slots == 1);
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assert(nir_src_as_uint(*nir_get_io_offset_src(load)) == 0);
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nir_intrinsic_instr *bary;
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switch (load->intrinsic) {
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case nir_intrinsic_load_input:
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bary = NULL;
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break;
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case nir_intrinsic_load_interpolated_input:
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/* Cannot interpolate ints */
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assert(nir_alu_type_get_base_type(dest_type) == nir_type_float);
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bary = nir_src_as_intrinsic(load->src[0]);
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break;
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default:
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UNREACHABLE("Already handled");
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}
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b->cursor = nir_before_instr(&load->instr);
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const unsigned component = nir_intrinsic_component(load);
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const unsigned load_comps = load->num_components + component;
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const struct pan_varying_slot *slot = NULL;
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bool use_ld_var_buf = false;
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if (ctx->varying_layout && ctx->arch >= 9) {
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pan_varying_layout_require_layout(ctx->varying_layout);
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slot = pan_varying_layout_find_slot(ctx->varying_layout, sem.location);
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assert(slot);
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use_ld_var_buf = slot->offset < pan_ld_var_buf_off_size(ctx->arch);
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}
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nir_def *res;
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if (use_ld_var_buf) {
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const nir_alu_type src_type = slot->alu_type;
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nir_def *offset_B = nir_imm_int(b, slot->offset);
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if (load->intrinsic == nir_intrinsic_load_interpolated_input) {
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res = nir_load_var_buf_pan(b, load_comps, load->def.bit_size,
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offset_B, &bary->def,
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.src_type = src_type,
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.io_semantics = sem);
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} else {
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res = nir_load_var_buf_flat_pan(b, load_comps, load->def.bit_size,
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offset_B,
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.src_type = src_type,
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.io_semantics = sem);
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}
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} else {
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ctx->info->bifrost.uses_ld_var = true;
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const uint32_t base = nir_intrinsic_base(load);
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nir_def *idx = nir_imm_int(b, base);
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if (load->intrinsic == nir_intrinsic_load_interpolated_input) {
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res = nir_load_var_pan(b, load_comps, load->def.bit_size,
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idx, &bary->def,
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.dest_type = dest_type,
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.io_semantics = sem);
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} else {
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res = nir_load_var_flat_pan(b, load_comps, load->def.bit_size, idx,
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.dest_type = dest_type,
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.io_semantics = sem);
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}
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}
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if (component > 0) {
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unsigned swiz[NIR_MAX_VEC_COMPONENTS] = {0, };
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for (unsigned c = 0; c < load->num_components; c++)
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swiz[c] = component + c;
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res = nir_swizzle(b, res, swiz, load->num_components);
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}
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nir_def_replace(&load->def, res);
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return true;
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}
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bool
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pan_nir_lower_fs_inputs(nir_shader *shader, unsigned gpu_id,
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const struct pan_varying_layout *varying_layout,
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struct pan_shader_info *info)
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{
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const struct lower_fs_inputs_ctx ctx = {
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.arch = pan_arch(gpu_id),
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.varying_layout = varying_layout,
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.info = info,
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};
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return nir_shader_intrinsics_pass(shader, lower_fs_input_load,
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nir_metadata_control_flow,
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(void *)&ctx);
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}
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