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ir3: Add missing cat5 encoding to asm parser

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We were missing the case where there is a sampler and texture but the
texture offset is encoded in a1.x.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18840>
This commit is contained in:
Connor Abbott 2022-09-26 18:40:53 +02:00 • committed by Marge Bot
parent dcab399a17
commit 66b9c05bb9
2 changed files with 2 additions and 0 deletions
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1
src/freedreno/ir3/ir3_parser.y
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@ -1076,6 +1076,7 @@ cat5_a1: src_reg { instr->flags |= IR3_INSTR_A1EN; }
cat5_instr: cat5_opc_dsxypp cat5_flags dst_reg ',' src_reg
| cat5_opc cat5_flags cat5_type dst_reg ',' src_reg ',' src_reg ',' src_reg
| cat5_opc cat5_flags cat5_type dst_reg ',' src_reg ',' src_reg ',' cat5_samp ',' cat5_tex
| cat5_opc cat5_flags cat5_type dst_reg ',' src_reg ',' src_reg ',' cat5_samp ',' cat5_a1
| cat5_opc cat5_flags cat5_type dst_reg ',' src_reg ',' src_reg ',' cat5_samp
| cat5_opc cat5_flags cat5_type dst_reg ',' src_reg ',' src_reg ',' cat5_tex
| cat5_opc cat5_flags cat5_type dst_reg ',' src_reg ',' src_reg

1
src/freedreno/ir3/tests/disasm.c
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@ -167,6 +167,7 @@ static const struct test {
INSTR_6XX(a0c81f00_e0200005, "sam.base0 (f32)(xyzw)r0.x, r0.z, s#1, a1.x"),
INSTR_6XX(a0c81108_e2000001, "sam.base0 (f32)(x)r2.x, r0.x, s#16, a1.x"),
INSTR_6XX(a048d107_cc080a07, "isaml.base3 (s32)(x)r1.w, r0.w, r1.y, s#0, t#6"),
INSTR_6XX(a048d107_e0080a07, "isaml.base3 (s32)(x)r1.w, r0.w, r1.y, s#0, a1.x"),
/* dEQP-VK.subgroups.arithmetic.compute.subgroupadd_float */