fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-09 04:38:03 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

anv: Drop depth cache flush requirement after depth clear/resolve

Browse source 
From Bspec 46959, a programming note applicable to Gfx12+:

   "Since HZ_OP has to be sent twice (first time set the clear/resolve
   state and 2nd time to clear the state), and HW internally flushes the
   depth cache on HZ_OP, there is no need to explicitly send a Depth
   Cache flush after Clear or Resolve."

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24027>
This commit is contained in:
Sagar Ghuge 2023-07-06 09:29:31 -07:00 • committed by Marge Bot
parent bcae312819
commit 66a6f48747
1 changed files with 13 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

17
src/intel/vulkan/anv_blorp.c
View file

@ -1562,11 +1562,20 @@ anv_fast_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer,
* Even though the PRM provides a bunch of conditions under which this is
* supposedly unnecessary, we choose to perform the flush unconditionally
* just to be safe.
*
* From Bspec 46959, a programming note applicable to Gfx12+:
*
* "Since HZ_OP has to be sent twice (first time set the clear/resolve state
* and 2nd time to clear the state), and HW internally flushes the depth
* cache on HZ_OP, there is no need to explicitly send a Depth Cache flush
* after Clear or Resolve."
*/
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
ANV_PIPE_DEPTH_STALL_BIT,
"after clear hiz");
if (cmd_buffer->device->info->verx10 < 120) {
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
ANV_PIPE_DEPTH_STALL_BIT,
"after clear hiz");
}
}
static bool