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ir3: Fix shared reg delay

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Based on computerator experiments, this is actually 6, including for
movmsk.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>
This commit is contained in:
Connor Abbott 2021-05-28 15:41:56 +02:00 • committed by Marge Bot
parent b1b4ce7be2
commit 66a275d50f
1 changed files with 1 additions and 4 deletions
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5
src/freedreno/ir3/ir3_delay.c
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@ -83,16 +83,13 @@ ir3_delayslots(struct ir3_instruction *assigner,
if (is_sfu(assigner) || is_tex(assigner) || is_mem(assigner))
return 0;
if (assigner->opc == OPC_MOVMSK)
return 4;
/* As far as we know, shader outputs don't need any delay. */
if (consumer->opc == OPC_END || consumer->opc == OPC_CHMASK)
return 0;
/* assigner must be alu: */
if (is_flow(consumer) || is_sfu(consumer) || is_tex(consumer) ||
is_mem(consumer)) {
is_mem(consumer) || (assigner->dsts[0]->flags & IR3_REG_SHARED)) {
return 6;
} else {
/* In mergedregs mode, there is an extra 2-cycle penalty when half of