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i965/fs: Fix message setup for SIMD8 spills.

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In the SIMD16 spilling changes, I replaced a "1" in the spill path with
"mlen", but obviously it wasn't mlen before because spills have the g0
header along with the payload. The interface I was trying to use was
asking for how many physical regs we're writing, so we're looking for "1"
or "2".

I'm guessing this actually passed piglit because the high 8 bits of the
execution mask in SIMD8 mode are all 0s.

Cc: "10.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
(cherry picked from commit 7c90947a0b)
This commit is contained in:
Eric Anholt 2013-11-04 22:56:33 -08:00 • committed by Ian Romanick
parent 229ee20460
commit 6640147463
1 changed files with 1 additions and 1 deletions
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src/mesa/drivers/dri/i965/brw_fs_generator.cpp
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@ -757,7 +757,7 @@ fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
retype(src, BRW_REGISTER_TYPE_UD));
brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
inst->mlen, inst->offset);
dispatch_width / 8, inst->offset);
}
void