mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-05 07:28:11 +02:00
i965/fs: Add initial support for 16-wide dispatch on gen6.
At this point it doesn't do uniforms, which have to be laid out the same between 8 and 16. Other than that, it supports everything but flow control, which was the thing that forced us to choose 8-wide for general GLSL support. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Eric Anholt
parent
76b7a0c1af
commit
662f1b48bd
6 changed files with 233 additions and 104 deletions
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@ -204,13 +204,16 @@ struct brw_wm_prog_data {
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GLuint urb_read_length;
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GLuint first_curbe_grf;
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GLuint first_curbe_grf_16;
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GLuint total_grf;
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GLuint total_grf_16;
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GLuint total_scratch;
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GLuint nr_params; /**< number of float params/constants */
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GLuint nr_pull_params;
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GLboolean error;
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int dispatch_width;
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uint32_t prog_offset_16;
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/* Pointer to tracked values (only valid once
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* _mesa_load_state_parameters has been called at runtime).
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@ -194,6 +194,32 @@ fs_visitor::fail(const char *format, ...)
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}
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}
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void
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fs_visitor::push_force_uncompressed()
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{
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force_uncompressed_stack++;
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}
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void
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fs_visitor::pop_force_uncompressed()
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{
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force_uncompressed_stack--;
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assert(force_uncompressed_stack >= 0);
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}
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void
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fs_visitor::push_force_sechalf()
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{
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force_sechalf_stack++;
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}
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void
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fs_visitor::pop_force_sechalf()
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{
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force_sechalf_stack--;
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assert(force_sechalf_stack >= 0);
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}
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/**
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* Returns how many MRFs an FS opcode will write over.
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*
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@ -1738,6 +1764,10 @@ fs_visitor::visit(ir_if *ir)
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{
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fs_inst *inst;
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if (c->dispatch_width == 16) {
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fail("Can't support (non-uniform) control flow on 16-wide\n");
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}
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/* Don't point the annotation at the if statement, because then it plus
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* the then and else blocks get printed.
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*/
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@ -1778,6 +1808,10 @@ fs_visitor::visit(ir_loop *ir)
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{
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fs_reg counter = reg_undef;
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if (c->dispatch_width == 16) {
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fail("Can't support (non-uniform) control flow on 16-wide\n");
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}
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if (ir->counter) {
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this->base_ir = ir->counter;
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ir->counter->accept(this);
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@ -1881,6 +1915,11 @@ fs_visitor::emit(fs_inst inst)
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fs_inst *list_inst = new(mem_ctx) fs_inst;
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*list_inst = inst;
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if (force_uncompressed_stack > 0)
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list_inst->force_uncompressed = true;
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else if (force_sechalf_stack > 0)
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list_inst->force_sechalf = true;
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list_inst->annotation = this->current_annotation;
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list_inst->ir = this->base_ir;
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@ -2006,6 +2045,7 @@ fs_visitor::emit_fb_writes()
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this->current_annotation = "FB write header";
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GLboolean header_present = GL_TRUE;
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int nr = 0;
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int reg_width = c->dispatch_width / 8;
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if (intel->gen >= 6 &&
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!this->kill_emitted &&
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@ -2019,31 +2059,44 @@ fs_visitor::emit_fb_writes()
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}
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if (c->aa_dest_stencil_reg) {
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push_force_uncompressed();
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emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
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fs_reg(brw_vec8_grf(c->aa_dest_stencil_reg, 0)));
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pop_force_uncompressed();
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}
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/* Reserve space for color. It'll be filled in per MRT below. */
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int color_mrf = nr;
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nr += 4;
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nr += 4 * reg_width;
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if (c->source_depth_to_render_target) {
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if (intel->gen == 6 && c->dispatch_width == 16) {
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/* For outputting oDepth on gen6, SIMD8 writes have to be
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* used. This would require 8-wide moves of each half to
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* message regs, kind of like pre-gen5 SIMD16 FB writes.
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* Just bail on doing so for now.
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*/
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fail("Missing support for simd16 depth writes on gen6\n");
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}
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if (c->computes_depth) {
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/* Hand over gl_FragDepth. */
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assert(this->frag_depth);
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fs_reg depth = *(variable_storage(this->frag_depth));
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emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++), depth);
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emit(BRW_OPCODE_MOV, fs_reg(MRF, nr), depth);
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} else {
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/* Pass through the payload depth. */
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emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
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emit(BRW_OPCODE_MOV, fs_reg(MRF, nr),
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fs_reg(brw_vec8_grf(c->source_depth_reg, 0)));
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}
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nr += reg_width;
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}
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if (c->dest_depth_reg) {
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emit(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
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emit(BRW_OPCODE_MOV, fs_reg(MRF, nr),
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fs_reg(brw_vec8_grf(c->dest_depth_reg, 0)));
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nr += reg_width;
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}
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fs_reg color = reg_undef;
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@ -2060,7 +2113,7 @@ fs_visitor::emit_fb_writes()
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target);
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if (this->frag_color || this->frag_data) {
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for (int i = 0; i < 4; i++) {
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emit(BRW_OPCODE_MOV, fs_reg(MRF, color_mrf + i), color);
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emit(BRW_OPCODE_MOV, fs_reg(MRF, color_mrf + i * reg_width), color);
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color.reg_offset++;
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}
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}
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@ -2144,7 +2197,7 @@ fs_visitor::generate_fb_write(fs_inst *inst)
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brw_pop_insn_state(p);
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brw_fb_WRITE(p,
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8, /* dispatch_width */
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c->dispatch_width,
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inst->base_mrf,
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implied_header,
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inst->target,
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@ -2608,8 +2661,12 @@ fs_visitor::setup_paramvalues_refs()
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void
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fs_visitor::assign_curb_setup()
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{
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c->prog_data.first_curbe_grf = c->nr_payload_regs;
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c->prog_data.curb_read_length = ALIGN(c->prog_data.nr_params, 8) / 8;
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if (c->dispatch_width == 8) {
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c->prog_data.first_curbe_grf = c->nr_payload_regs;
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} else {
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c->prog_data.first_curbe_grf_16 = c->nr_payload_regs;
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}
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/* Map the offsets in the UNIFORM file to fixed HW regs. */
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foreach_iter(exec_list_iterator, iter, this->instructions) {
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@ -2618,7 +2675,7 @@ fs_visitor::assign_curb_setup()
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for (unsigned int i = 0; i < 3; i++) {
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if (inst->src[i].file == UNIFORM) {
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int constant_nr = inst->src[i].hw_reg + inst->src[i].reg_offset;
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struct brw_reg brw_reg = brw_vec1_grf(c->prog_data.first_curbe_grf +
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struct brw_reg brw_reg = brw_vec1_grf(c->nr_payload_regs +
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constant_nr / 8,
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constant_nr % 8);
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@ -2670,7 +2727,7 @@ fs_visitor::calculate_urb_setup()
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void
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fs_visitor::assign_urb_setup()
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{
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int urb_start = c->prog_data.first_curbe_grf + c->prog_data.curb_read_length;
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int urb_start = c->nr_payload_regs + c->prog_data.curb_read_length;
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/* Offset all the urb_setup[] index by the actual position of the
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* setup regs, now that the location of the constants has been chosen.
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@ -3516,7 +3573,7 @@ static struct brw_reg brw_reg_from_fs_reg(fs_reg *reg)
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void
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fs_visitor::generate_code()
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{
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int last_native_inst = 0;
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int last_native_inst = p->nr_insn;
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const char *last_annotation_string = NULL;
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ir_instruction *last_annotation_ir = NULL;
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@ -3532,8 +3589,8 @@ fs_visitor::generate_code()
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if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
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printf("Native code for fragment shader %d:\n",
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ctx->Shader.CurrentFragmentProgram->Name);
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printf("Native code for fragment shader %d (%d-wide dispatch):\n",
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ctx->Shader.CurrentFragmentProgram->Name, c->dispatch_width);
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}
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foreach_iter(exec_list_iterator, iter, this->instructions) {
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@ -3566,6 +3623,14 @@ fs_visitor::generate_code()
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brw_set_predicate_inverse(p, inst->predicate_inverse);
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brw_set_saturate(p, inst->saturate);
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if (inst->force_uncompressed || c->dispatch_width == 8) {
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brw_set_compression_control(p, BRW_COMPRESSION_NONE);
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} else if (inst->force_sechalf) {
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brw_set_compression_control(p, BRW_COMPRESSION_2NDHALF);
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} else {
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brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
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}
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switch (inst->opcode) {
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case BRW_OPCODE_MOV:
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brw_MOV(p, dst, src[0]);
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@ -3804,7 +3869,111 @@ fs_visitor::generate_code()
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}
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}
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GLboolean
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bool
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fs_visitor::run()
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{
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uint32_t prog_offset_16 = 0;
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brw_wm_payload_setup(brw, c);
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if (c->dispatch_width == 16) {
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if (c->prog_data.curb_read_length) {
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/* Haven't hooked in support for uniforms through the 16-wide
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* version yet.
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*/
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return GL_FALSE;
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}
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/* align to 64 byte boundary. */
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while ((c->func.nr_insn * sizeof(struct brw_instruction)) % 64) {
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brw_NOP(p);
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}
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/* Save off the start of this 16-wide program in case we succeed. */
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prog_offset_16 = c->func.nr_insn * sizeof(struct brw_instruction);
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brw_set_compression_control(p, BRW_COMPRESSION_COMPRESSED);
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}
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if (0) {
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emit_dummy_fs();
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} else {
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calculate_urb_setup();
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if (intel->gen < 6)
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emit_interpolation_setup_gen4();
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else
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emit_interpolation_setup_gen6();
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/* Generate FS IR for main(). (the visitor only descends into
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* functions called "main").
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*/
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foreach_iter(exec_list_iterator, iter, *shader->ir) {
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ir_instruction *ir = (ir_instruction *)iter.get();
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base_ir = ir;
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ir->accept(this);
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}
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emit_fb_writes();
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split_virtual_grfs();
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setup_paramvalues_refs();
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setup_pull_constants();
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bool progress;
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do {
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progress = false;
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progress = remove_duplicate_mrf_writes() || progress;
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progress = propagate_constants() || progress;
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progress = register_coalesce() || progress;
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progress = compute_to_mrf() || progress;
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progress = dead_code_eliminate() || progress;
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} while (progress);
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schedule_instructions();
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assign_curb_setup();
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assign_urb_setup();
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if (0) {
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/* Debug of register spilling: Go spill everything. */
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int virtual_grf_count = virtual_grf_next;
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for (int i = 1; i < virtual_grf_count; i++) {
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spill_reg(i);
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}
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}
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if (0)
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assign_regs_trivial();
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else {
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while (!assign_regs()) {
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if (failed)
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break;
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}
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}
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}
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assert(force_uncompressed_stack == 0);
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assert(force_sechalf_stack == 0);
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if (!failed)
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generate_code();
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if (failed)
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return GL_FALSE;
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if (c->dispatch_width == 8) {
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c->prog_data.total_grf = grf_used;
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} else {
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c->prog_data.total_grf_16 = grf_used;
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c->prog_data.prog_offset_16 = prog_offset_16;
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}
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return !failed;
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}
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bool
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brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c)
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{
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struct intel_context *intel = &brw->intel;
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@ -3812,20 +3981,12 @@ brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c)
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struct gl_shader_program *prog = ctx->Shader.CurrentFragmentProgram;
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if (!prog)
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return GL_FALSE;
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return false;
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struct brw_shader *shader =
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(brw_shader *) prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
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if (!shader)
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return GL_FALSE;
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/* We always use 8-wide mode, at least for now. For one, flow
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* control only works in 8-wide. Also, when we're fragment shader
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* bound, we're almost always under register pressure as well, so
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* 8-wide would save us from the performance cliff of spilling
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* regs.
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*/
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c->dispatch_width = 8;
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return false;
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if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
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printf("GLSL IR for native fragment shader %d:\n", prog->Name);
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@ -3835,77 +3996,22 @@ brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c)
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/* Now the main event: Visit the shader IR and generate our FS IR for it.
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*/
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c->dispatch_width = 8;
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fs_visitor v(c, shader);
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if (0) {
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v.emit_dummy_fs();
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} else {
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v.calculate_urb_setup();
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if (intel->gen < 6)
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v.emit_interpolation_setup_gen4();
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else
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v.emit_interpolation_setup_gen6();
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/* Generate FS IR for main(). (the visitor only descends into
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* functions called "main").
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*/
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foreach_iter(exec_list_iterator, iter, *shader->ir) {
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ir_instruction *ir = (ir_instruction *)iter.get();
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v.base_ir = ir;
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ir->accept(&v);
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}
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v.emit_fb_writes();
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v.split_virtual_grfs();
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v.setup_paramvalues_refs();
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v.setup_pull_constants();
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bool progress;
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do {
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progress = false;
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progress = v.remove_duplicate_mrf_writes() || progress;
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progress = v.propagate_constants() || progress;
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progress = v.register_coalesce() || progress;
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progress = v.compute_to_mrf() || progress;
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progress = v.dead_code_eliminate() || progress;
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} while (progress);
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v.schedule_instructions();
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v.assign_curb_setup();
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v.assign_urb_setup();
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if (0) {
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/* Debug of register spilling: Go spill everything. */
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int virtual_grf_count = v.virtual_grf_next;
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for (int i = 1; i < virtual_grf_count; i++) {
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v.spill_reg(i);
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}
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}
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if (0)
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v.assign_regs_trivial();
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else {
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while (!v.assign_regs()) {
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if (v.failed)
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break;
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}
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}
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if (!v.run()) {
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/* FINISHME: Cleanly fail, test at link time, etc. */
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assert(!"not reached");
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return false;
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}
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if (!v.failed)
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v.generate_code();
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if (intel->gen >= 6) {
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c->dispatch_width = 16;
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fs_visitor v2(c, shader);
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v2.run();
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}
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assert(!v.failed); /* FINISHME: Cleanly fail, tested at link time, etc. */
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c->prog_data.dispatch_width = 8;
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if (v.failed)
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return GL_FALSE;
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c->prog_data.total_grf = v.grf_used;
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return GL_TRUE;
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return true;
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}
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@ -343,6 +343,8 @@ public:
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bool eot;
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bool header_present;
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bool shadow_compare;
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bool force_uncompressed;
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bool force_sechalf;
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uint32_t offset; /* spill/unspill offset */
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/** @{
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@ -405,6 +407,8 @@ public:
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this->live_intervals_valid = false;
|
||||
|
||||
this->kill_emitted = false;
|
||||
this->force_uncompressed_stack = 0;
|
||||
this->force_sechalf_stack = 0;
|
||||
}
|
||||
|
||||
~fs_visitor()
|
||||
|
|
@ -461,6 +465,7 @@ public:
|
|||
return emit(fs_inst(opcode, dst, src0, src1, src2));
|
||||
}
|
||||
|
||||
bool run();
|
||||
void setup_paramvalues_refs();
|
||||
void assign_curb_setup();
|
||||
void calculate_urb_setup();
|
||||
|
|
@ -481,6 +486,11 @@ public:
|
|||
void schedule_instructions();
|
||||
void fail(const char *msg, ...);
|
||||
|
||||
void push_force_uncompressed();
|
||||
void pop_force_uncompressed();
|
||||
void push_force_sechalf();
|
||||
void pop_force_sechalf();
|
||||
|
||||
void generate_code();
|
||||
void generate_fb_write(fs_inst *inst);
|
||||
void generate_pixel_xy(struct brw_reg dst, bool is_x);
|
||||
|
|
@ -568,6 +578,9 @@ public:
|
|||
fs_reg reg_null_cmp;
|
||||
|
||||
int grf_used;
|
||||
|
||||
int force_uncompressed_stack;
|
||||
int force_sechalf_stack;
|
||||
};
|
||||
|
||||
GLboolean brw_do_channel_expressions(struct exec_list *instructions);
|
||||
|
|
|
|||
|
|
@ -120,7 +120,7 @@ brw_wm_non_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c)
|
|||
brw_wm_emit(c);
|
||||
}
|
||||
|
||||
static void
|
||||
void
|
||||
brw_wm_payload_setup(struct brw_context *brw,
|
||||
struct brw_wm_compile *c)
|
||||
{
|
||||
|
|
@ -225,18 +225,13 @@ static void do_wm_prog( struct brw_context *brw,
|
|||
|
||||
brw_init_compile(brw, &c->func);
|
||||
|
||||
brw_wm_payload_setup(brw, c);
|
||||
|
||||
if (!brw_wm_fs_emit(brw, c)) {
|
||||
/*
|
||||
* Shader which use GLSL features such as flow control are handled
|
||||
* differently from "simple" shaders.
|
||||
*/
|
||||
/* Fallback for fixed function and ARB_fp shaders. */
|
||||
c->dispatch_width = 16;
|
||||
brw_wm_payload_setup(brw, c);
|
||||
brw_wm_non_glsl_emit(brw, c);
|
||||
c->prog_data.dispatch_width = 16;
|
||||
}
|
||||
c->prog_data.dispatch_width = c->dispatch_width;
|
||||
|
||||
/* Scratch space is used for register spilling */
|
||||
if (c->last_scratch) {
|
||||
|
|
@ -467,7 +462,7 @@ static void brw_prepare_wm_prog(struct brw_context *brw)
|
|||
struct brw_wm_prog_key key;
|
||||
struct brw_fragment_program *fp = (struct brw_fragment_program *)
|
||||
brw->fragment_program;
|
||||
|
||||
|
||||
brw_wm_populate_key(brw, &key);
|
||||
|
||||
/* Make an early check for the key.
|
||||
|
|
|
|||
|
|
@ -314,7 +314,7 @@ void brw_wm_print_program( struct brw_wm_compile *c,
|
|||
void brw_wm_lookup_iz(struct intel_context *intel,
|
||||
struct brw_wm_compile *c);
|
||||
|
||||
GLboolean brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c);
|
||||
bool brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c);
|
||||
|
||||
/* brw_wm_emit.c */
|
||||
void emit_alu1(struct brw_compile *p,
|
||||
|
|
@ -474,5 +474,7 @@ struct gl_shader_program *brw_new_shader_program(struct gl_context *ctx, GLuint
|
|||
|
||||
bool brw_color_buffer_write_enabled(struct brw_context *brw);
|
||||
bool brw_render_target_supported(gl_format format);
|
||||
void brw_wm_payload_setup(struct brw_context *brw,
|
||||
struct brw_wm_compile *c);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -143,14 +143,19 @@ upload_wm_state(struct brw_context *brw)
|
|||
dw2 |= (ALIGN(brw->wm.sampler_count, 4) / 4) << GEN6_WM_SAMPLER_COUNT_SHIFT;
|
||||
dw4 |= (brw->wm.prog_data->first_curbe_grf <<
|
||||
GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
|
||||
dw4 |= (brw->wm.prog_data->first_curbe_grf_16 <<
|
||||
GEN6_WM_DISPATCH_START_GRF_SHIFT_2);
|
||||
|
||||
dw5 |= (brw->wm_max_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT;
|
||||
|
||||
/* CACHE_NEW_WM_PROG */
|
||||
if (brw->wm.prog_data->dispatch_width == 8)
|
||||
if (brw->wm.prog_data->dispatch_width == 8) {
|
||||
dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
|
||||
else
|
||||
if (brw->wm.prog_data->prog_offset_16)
|
||||
dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
|
||||
} else {
|
||||
dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
|
||||
}
|
||||
|
||||
/* _NEW_LINE */
|
||||
if (ctx->Line.StippleFlag)
|
||||
|
|
@ -194,7 +199,12 @@ upload_wm_state(struct brw_context *brw)
|
|||
OUT_BATCH(dw5);
|
||||
OUT_BATCH(dw6);
|
||||
OUT_BATCH(0); /* kernel 1 pointer */
|
||||
OUT_BATCH(0); /* kernel 2 pointer */
|
||||
if (brw->wm.prog_data->prog_offset_16) {
|
||||
OUT_RELOC(brw->wm.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0,
|
||||
brw->wm.prog_data->prog_offset_16);
|
||||
} else {
|
||||
OUT_BATCH(0); /* kernel 2 pointer */
|
||||
}
|
||||
ADVANCE_BATCH();
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue