mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
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radeonsi: import r600_streamout from drivers/radeon
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
parent
ed7f27ded8
commit
65f2e33500
15 changed files with 181 additions and 177 deletions
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@ -8,7 +8,6 @@ C_SOURCES := \
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r600_pipe_common.h \
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r600_query.c \
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r600_query.h \
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r600_streamout.c \
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r600_test_dma.c \
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r600_texture.c \
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radeon_uvd.c \
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@ -296,21 +296,10 @@ void si_preflush_suspend_features(struct r600_common_context *ctx)
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/* suspend queries */
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if (!LIST_IS_EMPTY(&ctx->active_queries))
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si_suspend_queries(ctx);
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ctx->streamout.suspended = false;
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if (ctx->streamout.begin_emitted) {
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si_emit_streamout_end(ctx);
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ctx->streamout.suspended = true;
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}
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}
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void si_postflush_resume_features(struct r600_common_context *ctx)
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{
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if (ctx->streamout.suspended) {
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ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
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si_streamout_buffers_dirty(ctx);
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}
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/* resume queries */
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if (!LIST_IS_EMPTY(&ctx->active_queries))
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si_resume_queries(ctx);
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@ -647,7 +636,6 @@ bool si_common_context_init(struct r600_common_context *rctx,
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rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
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si_init_context_texture_functions(rctx);
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si_streamout_init(rctx);
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si_init_query_functions(rctx);
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si_init_msaa(&rctx->b);
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@ -497,43 +497,6 @@ struct r600_atom {
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unsigned short id;
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};
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struct r600_so_target {
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struct pipe_stream_output_target b;
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/* The buffer where BUFFER_FILLED_SIZE is stored. */
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struct r600_resource *buf_filled_size;
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unsigned buf_filled_size_offset;
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bool buf_filled_size_valid;
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unsigned stride_in_dw;
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};
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struct r600_streamout {
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struct r600_atom begin_atom;
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bool begin_emitted;
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unsigned enabled_mask;
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unsigned num_targets;
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struct r600_so_target *targets[PIPE_MAX_SO_BUFFERS];
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unsigned append_bitmask;
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bool suspended;
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/* External state which comes from the vertex shader,
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* it must be set explicitly when binding a shader. */
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uint16_t *stride_in_dw;
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unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
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/* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
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unsigned hw_enabled_mask;
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/* The state of VGT_STRMOUT_(CONFIG|EN). */
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struct r600_atom enable_atom;
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bool streamout_enabled;
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bool prims_gen_query_enabled;
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int num_prims_gen_queries;
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};
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struct r600_ring {
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struct radeon_winsys_cs *cs;
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void (*flush)(void *ctx, unsigned flags,
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@ -578,9 +541,6 @@ struct r600_common_context {
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uint64_t vram;
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uint64_t gtt;
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/* States. */
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struct r600_streamout streamout;
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/* Additional context states. */
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unsigned flags; /* flush flags */
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@ -790,17 +750,6 @@ void si_init_query_functions(struct r600_common_context *rctx);
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void si_suspend_queries(struct r600_common_context *ctx);
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void si_resume_queries(struct r600_common_context *ctx);
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/* r600_streamout.c */
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void si_streamout_buffers_dirty(struct r600_common_context *rctx);
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void si_common_set_streamout_targets(struct pipe_context *ctx,
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unsigned num_targets,
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struct pipe_stream_output_target **targets,
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const unsigned *offset);
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void si_emit_streamout_end(struct r600_common_context *rctx);
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void si_update_prims_generated_query_state(struct r600_common_context *rctx,
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unsigned type, int diff);
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void si_streamout_init(struct r600_common_context *rctx);
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/* r600_test_dma.c */
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void si_test_dma(struct r600_common_screen *rscreen);
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@ -900,12 +849,6 @@ r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r
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}
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}
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static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
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{
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return rctx->streamout.streamout_enabled ||
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rctx->streamout.prims_gen_query_enabled;
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}
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#define SQ_TEX_XY_FILTER_POINT 0x00
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#define SQ_TEX_XY_FILTER_BILINEAR 0x01
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#define SQ_TEX_XY_FILTER_ANISO_POINT 0x02
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@ -29,6 +29,10 @@
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#include "os/os_time.h"
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#include "tgsi/tgsi_text.h"
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/* TODO: remove this: */
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void si_update_prims_generated_query_state(struct r600_common_context *rctx,
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unsigned type, int diff);
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#define R600_MAX_STREAMS 4
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struct r600_hw_query_params {
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@ -30,6 +30,7 @@ C_SOURCES := \
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si_state_binning.c \
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si_state_draw.c \
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si_state_shaders.c \
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si_state_streamout.c \
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si_state_viewport.c \
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si_state.h \
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si_uvd.c
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@ -58,8 +58,8 @@ static void si_blitter_begin(struct pipe_context *ctx, enum si_blitter_op op)
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util_blitter_save_tessctrl_shader(sctx->blitter, sctx->tcs_shader.cso);
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util_blitter_save_tesseval_shader(sctx->blitter, sctx->tes_shader.cso);
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util_blitter_save_geometry_shader(sctx->blitter, sctx->gs_shader.cso);
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util_blitter_save_so_targets(sctx->blitter, sctx->b.streamout.num_targets,
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(struct pipe_stream_output_target**)sctx->b.streamout.targets);
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util_blitter_save_so_targets(sctx->blitter, sctx->streamout.num_targets,
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(struct pipe_stream_output_target**)sctx->streamout.targets);
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util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
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if (op & SI_SAVE_FRAGMENT_STATE) {
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@ -1373,11 +1373,11 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
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struct si_context *sctx = (struct si_context *)ctx;
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struct si_buffer_resources *buffers = &sctx->rw_buffers;
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struct si_descriptors *descs = &sctx->descriptors[SI_DESCS_RW_BUFFERS];
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unsigned old_num_targets = sctx->b.streamout.num_targets;
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unsigned old_num_targets = sctx->streamout.num_targets;
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unsigned i, bufidx;
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/* We are going to unbind the buffers. Mark which caches need to be flushed. */
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if (sctx->b.streamout.num_targets && sctx->b.streamout.begin_emitted) {
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if (sctx->streamout.num_targets && sctx->streamout.begin_emitted) {
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/* Since streamout uses vector writes which go through TC L2
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* and most other clients can use TC L2 as well, we don't need
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* to flush it.
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@ -1387,9 +1387,9 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
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* cases. Thus, flag the TC L2 dirtiness in the resource and
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* handle it at draw call time.
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*/
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for (i = 0; i < sctx->b.streamout.num_targets; i++)
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if (sctx->b.streamout.targets[i])
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r600_resource(sctx->b.streamout.targets[i]->b.buffer)->TC_L2_dirty = true;
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for (i = 0; i < sctx->streamout.num_targets; i++)
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if (sctx->streamout.targets[i])
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r600_resource(sctx->streamout.targets[i]->b.buffer)->TC_L2_dirty = true;
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/* Invalidate the scalar cache in case a streamout buffer is
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* going to be used as a constant buffer.
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@ -1650,11 +1650,11 @@ static void si_rebind_buffer(struct pipe_context *ctx, struct pipe_resource *buf
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true);
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/* Update the streamout state. */
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if (sctx->b.streamout.begin_emitted)
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si_emit_streamout_end(&sctx->b);
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sctx->b.streamout.append_bitmask =
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sctx->b.streamout.enabled_mask;
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si_streamout_buffers_dirty(&sctx->b);
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if (sctx->streamout.begin_emitted)
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si_emit_streamout_end(sctx);
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sctx->streamout.append_bitmask =
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sctx->streamout.enabled_mask;
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si_streamout_buffers_dirty(sctx);
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}
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}
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@ -100,6 +100,12 @@ void si_context_gfx_flush(void *context, unsigned flags,
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si_preflush_suspend_features(&ctx->b);
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ctx->streamout.suspended = false;
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if (ctx->streamout.begin_emitted) {
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si_emit_streamout_end(ctx);
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ctx->streamout.suspended = true;
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}
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ctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH |
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SI_CONTEXT_PS_PARTIAL_FLUSH;
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@ -243,7 +249,7 @@ void si_begin_new_cs(struct si_context *ctx)
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si_mark_atom_dirty(ctx, &ctx->dpbb_state);
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si_mark_atom_dirty(ctx, &ctx->stencil_ref.atom);
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si_mark_atom_dirty(ctx, &ctx->spi_map);
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si_mark_atom_dirty(ctx, &ctx->b.streamout.enable_atom);
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si_mark_atom_dirty(ctx, &ctx->streamout.enable_atom);
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si_mark_atom_dirty(ctx, &ctx->b.render_cond_atom);
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si_all_descriptors_begin_new_cs(ctx);
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si_all_resident_buffers_begin_new_cs(ctx);
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@ -260,6 +266,11 @@ void si_begin_new_cs(struct si_context *ctx)
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&ctx->scratch_buffer->b.b);
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}
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if (ctx->streamout.suspended) {
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ctx->streamout.append_bitmask = ctx->streamout.enabled_mask;
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si_streamout_buffers_dirty(ctx);
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}
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si_postflush_resume_features(&ctx->b);
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assert(!ctx->b.gfx.cs->prev_dw);
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@ -205,6 +205,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
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si_init_compute_functions(sctx);
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si_init_cp_dma_functions(sctx);
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si_init_debug_functions(sctx);
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si_init_streamout_functions(sctx);
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if (sscreen->b.info.has_hw_decode) {
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sctx->b.b.create_video_codec = si_uvd_create_decoder;
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@ -255,6 +255,43 @@ struct si_sample_mask {
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uint16_t sample_mask;
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};
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struct si_streamout_target {
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struct pipe_stream_output_target b;
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/* The buffer where BUFFER_FILLED_SIZE is stored. */
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struct r600_resource *buf_filled_size;
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unsigned buf_filled_size_offset;
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bool buf_filled_size_valid;
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unsigned stride_in_dw;
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};
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struct si_streamout {
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struct r600_atom begin_atom;
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bool begin_emitted;
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unsigned enabled_mask;
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unsigned num_targets;
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struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
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unsigned append_bitmask;
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bool suspended;
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/* External state which comes from the vertex shader,
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* it must be set explicitly when binding a shader. */
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uint16_t *stride_in_dw;
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unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
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/* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
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unsigned hw_enabled_mask;
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/* The state of VGT_STRMOUT_(CONFIG|EN). */
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struct r600_atom enable_atom;
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bool streamout_enabled;
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bool prims_gen_query_enabled;
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int num_prims_gen_queries;
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};
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/* A shader state consists of the shader selector, which is a constant state
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* object shared by multiple contexts and shouldn't be modified, and
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* the current shader variant selected for this context.
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@ -359,6 +396,7 @@ struct si_context {
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struct si_stencil_ref stencil_ref;
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struct r600_atom spi_map;
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struct si_scissors scissors;
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struct si_streamout streamout;
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struct si_viewports viewports;
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/* Precomputed states. */
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@ -644,6 +682,12 @@ static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
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return vs->current ? vs->current : NULL;
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}
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static inline bool si_get_strmout_en(struct si_context *sctx)
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{
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return sctx->streamout.streamout_enabled ||
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sctx->streamout.prims_gen_query_enabled;
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}
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static inline unsigned
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si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
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{
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@ -4407,8 +4407,8 @@ static void si_init_config(struct si_context *sctx);
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void si_init_state_functions(struct si_context *sctx)
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{
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si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
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si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
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si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
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si_init_external_atom(sctx, &sctx->streamout.begin_atom, &sctx->atoms.s.streamout_begin);
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si_init_external_atom(sctx, &sctx->streamout.enable_atom, &sctx->atoms.s.streamout_enable);
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si_init_external_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors);
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si_init_external_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports);
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@ -423,6 +423,17 @@ void si_draw_rectangle(struct blitter_context *blitter,
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const union blitter_attrib *attrib);
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void si_trace_emit(struct si_context *sctx);
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/* si_state_streamout.c */
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void si_streamout_buffers_dirty(struct si_context *sctx);
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void si_common_set_streamout_targets(struct pipe_context *ctx,
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unsigned num_targets,
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struct pipe_stream_output_target **targets,
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const unsigned *offset);
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void si_emit_streamout_end(struct si_context *sctx);
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void si_update_prims_generated_query_state(struct si_context *sctx,
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unsigned type, int diff);
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void si_init_streamout_functions(struct si_context *sctx);
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static inline unsigned
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si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
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@ -652,8 +652,8 @@ static void si_emit_draw_packets(struct si_context *sctx,
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uint64_t index_va = 0;
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if (info->count_from_stream_output) {
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struct r600_so_target *t =
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(struct r600_so_target*)info->count_from_stream_output;
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struct si_streamout_target *t =
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(struct si_streamout_target*)info->count_from_stream_output;
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uint64_t va = t->buf_filled_size->gpu_address +
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t->buf_filled_size_offset;
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@ -1486,7 +1486,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
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if ((sctx->b.family == CHIP_HAWAII ||
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sctx->b.family == CHIP_TONGA ||
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sctx->b.family == CHIP_FIJI) &&
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r600_get_strmout_en(&sctx->b)) {
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si_get_strmout_en(sctx)) {
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sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
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}
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@ -2252,9 +2252,9 @@ static void si_update_streamout_state(struct si_context *sctx)
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if (!shader_with_so)
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return;
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sctx->b.streamout.enabled_stream_buffers_mask =
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sctx->streamout.enabled_stream_buffers_mask =
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shader_with_so->enabled_streamout_buffer_mask;
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sctx->b.streamout.stride_in_dw = shader_with_so->so.stride;
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sctx->streamout.stride_in_dw = shader_with_so->so.stride;
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}
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static void si_update_clip_regs(struct si_context *sctx,
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@ -24,29 +24,30 @@
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*
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*/
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#include "r600_pipe_common.h"
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#include "r600_cs.h"
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#include "si_pipe.h"
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#include "si_state.h"
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#include "radeon/r600_cs.h"
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#include "util/u_memory.h"
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static void r600_set_streamout_enable(struct r600_common_context *rctx, bool enable);
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static void si_set_streamout_enable(struct si_context *sctx, bool enable);
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static struct pipe_stream_output_target *
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r600_create_so_target(struct pipe_context *ctx,
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struct pipe_resource *buffer,
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unsigned buffer_offset,
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unsigned buffer_size)
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si_create_so_target(struct pipe_context *ctx,
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struct pipe_resource *buffer,
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unsigned buffer_offset,
|
||||
unsigned buffer_size)
|
||||
{
|
||||
struct r600_common_context *rctx = (struct r600_common_context *)ctx;
|
||||
struct r600_so_target *t;
|
||||
struct si_context *sctx = (struct si_context *)ctx;
|
||||
struct si_streamout_target *t;
|
||||
struct r600_resource *rbuffer = (struct r600_resource*)buffer;
|
||||
|
||||
t = CALLOC_STRUCT(r600_so_target);
|
||||
t = CALLOC_STRUCT(si_streamout_target);
|
||||
if (!t) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
u_suballocator_alloc(rctx->allocator_zeroed_memory, 4, 4,
|
||||
u_suballocator_alloc(sctx->b.allocator_zeroed_memory, 4, 4,
|
||||
&t->buf_filled_size_offset,
|
||||
(struct pipe_resource**)&t->buf_filled_size);
|
||||
if (!t->buf_filled_size) {
|
||||
|
|
@ -65,22 +66,22 @@ r600_create_so_target(struct pipe_context *ctx,
|
|||
return &t->b;
|
||||
}
|
||||
|
||||
static void r600_so_target_destroy(struct pipe_context *ctx,
|
||||
struct pipe_stream_output_target *target)
|
||||
static void si_so_target_destroy(struct pipe_context *ctx,
|
||||
struct pipe_stream_output_target *target)
|
||||
{
|
||||
struct r600_so_target *t = (struct r600_so_target*)target;
|
||||
struct si_streamout_target *t = (struct si_streamout_target*)target;
|
||||
pipe_resource_reference(&t->b.buffer, NULL);
|
||||
r600_resource_reference(&t->buf_filled_size, NULL);
|
||||
FREE(t);
|
||||
}
|
||||
|
||||
void si_streamout_buffers_dirty(struct r600_common_context *rctx)
|
||||
void si_streamout_buffers_dirty(struct si_context *sctx)
|
||||
{
|
||||
if (!rctx->streamout.enabled_mask)
|
||||
if (!sctx->streamout.enabled_mask)
|
||||
return;
|
||||
|
||||
rctx->set_atom_dirty(rctx, &rctx->streamout.begin_atom, true);
|
||||
r600_set_streamout_enable(rctx, true);
|
||||
si_mark_atom_dirty(sctx, &sctx->streamout.begin_atom);
|
||||
si_set_streamout_enable(sctx, true);
|
||||
}
|
||||
|
||||
void si_common_set_streamout_targets(struct pipe_context *ctx,
|
||||
|
|
@ -88,18 +89,18 @@ void si_common_set_streamout_targets(struct pipe_context *ctx,
|
|||
struct pipe_stream_output_target **targets,
|
||||
const unsigned *offsets)
|
||||
{
|
||||
struct r600_common_context *rctx = (struct r600_common_context *)ctx;
|
||||
struct si_context *sctx = (struct si_context *)ctx;
|
||||
unsigned i;
|
||||
unsigned enabled_mask = 0, append_bitmask = 0;
|
||||
|
||||
/* Stop streamout. */
|
||||
if (rctx->streamout.num_targets && rctx->streamout.begin_emitted) {
|
||||
si_emit_streamout_end(rctx);
|
||||
if (sctx->streamout.num_targets && sctx->streamout.begin_emitted) {
|
||||
si_emit_streamout_end(sctx);
|
||||
}
|
||||
|
||||
/* Set the new targets. */
|
||||
for (i = 0; i < num_targets; i++) {
|
||||
pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->streamout.targets[i], targets[i]);
|
||||
pipe_so_target_reference((struct pipe_stream_output_target**)&sctx->streamout.targets[i], targets[i]);
|
||||
if (!targets[i])
|
||||
continue;
|
||||
|
||||
|
|
@ -108,30 +109,30 @@ void si_common_set_streamout_targets(struct pipe_context *ctx,
|
|||
if (offsets[i] == ((unsigned)-1))
|
||||
append_bitmask |= 1 << i;
|
||||
}
|
||||
for (; i < rctx->streamout.num_targets; i++) {
|
||||
pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->streamout.targets[i], NULL);
|
||||
for (; i < sctx->streamout.num_targets; i++) {
|
||||
pipe_so_target_reference((struct pipe_stream_output_target**)&sctx->streamout.targets[i], NULL);
|
||||
}
|
||||
|
||||
rctx->streamout.enabled_mask = enabled_mask;
|
||||
sctx->streamout.enabled_mask = enabled_mask;
|
||||
|
||||
rctx->streamout.num_targets = num_targets;
|
||||
rctx->streamout.append_bitmask = append_bitmask;
|
||||
sctx->streamout.num_targets = num_targets;
|
||||
sctx->streamout.append_bitmask = append_bitmask;
|
||||
|
||||
if (num_targets) {
|
||||
si_streamout_buffers_dirty(rctx);
|
||||
si_streamout_buffers_dirty(sctx);
|
||||
} else {
|
||||
rctx->set_atom_dirty(rctx, &rctx->streamout.begin_atom, false);
|
||||
r600_set_streamout_enable(rctx, false);
|
||||
si_set_atom_dirty(sctx, &sctx->streamout.begin_atom, false);
|
||||
si_set_streamout_enable(sctx, false);
|
||||
}
|
||||
}
|
||||
|
||||
static void r600_flush_vgt_streamout(struct r600_common_context *rctx)
|
||||
static void si_flush_vgt_streamout(struct si_context *sctx)
|
||||
{
|
||||
struct radeon_winsys_cs *cs = rctx->gfx.cs;
|
||||
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
|
||||
unsigned reg_strmout_cntl;
|
||||
|
||||
/* The register is at different places on different ASICs. */
|
||||
if (rctx->chip_class >= CIK) {
|
||||
if (sctx->b.chip_class >= CIK) {
|
||||
reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
|
||||
radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
|
||||
} else {
|
||||
|
|
@ -151,16 +152,17 @@ static void r600_flush_vgt_streamout(struct r600_common_context *rctx)
|
|||
radeon_emit(cs, 4); /* poll interval */
|
||||
}
|
||||
|
||||
static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r600_atom *atom)
|
||||
static void si_emit_streamout_begin(struct r600_common_context *rctx, struct r600_atom *atom)
|
||||
{
|
||||
struct radeon_winsys_cs *cs = rctx->gfx.cs;
|
||||
struct r600_so_target **t = rctx->streamout.targets;
|
||||
uint16_t *stride_in_dw = rctx->streamout.stride_in_dw;
|
||||
struct si_context *sctx = (struct si_context*)rctx;
|
||||
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
|
||||
struct si_streamout_target **t = sctx->streamout.targets;
|
||||
uint16_t *stride_in_dw = sctx->streamout.stride_in_dw;
|
||||
unsigned i;
|
||||
|
||||
r600_flush_vgt_streamout(rctx);
|
||||
si_flush_vgt_streamout(sctx);
|
||||
|
||||
for (i = 0; i < rctx->streamout.num_targets; i++) {
|
||||
for (i = 0; i < sctx->streamout.num_targets; i++) {
|
||||
if (!t[i])
|
||||
continue;
|
||||
|
||||
|
|
@ -174,7 +176,7 @@ static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r
|
|||
t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE (in DW) */
|
||||
radeon_emit(cs, stride_in_dw[i]); /* VTX_STRIDE (in DW) */
|
||||
|
||||
if (rctx->streamout.append_bitmask & (1 << i) && t[i]->buf_filled_size_valid) {
|
||||
if (sctx->streamout.append_bitmask & (1 << i) && t[i]->buf_filled_size_valid) {
|
||||
uint64_t va = t[i]->buf_filled_size->gpu_address +
|
||||
t[i]->buf_filled_size_offset;
|
||||
|
||||
|
|
@ -187,7 +189,7 @@ static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r
|
|||
radeon_emit(cs, va); /* src address lo */
|
||||
radeon_emit(cs, va >> 32); /* src address hi */
|
||||
|
||||
r600_emit_reloc(rctx, &rctx->gfx, t[i]->buf_filled_size,
|
||||
r600_emit_reloc(&sctx->b, &sctx->b.gfx, t[i]->buf_filled_size,
|
||||
RADEON_USAGE_READ, RADEON_PRIO_SO_FILLED_SIZE);
|
||||
} else {
|
||||
/* Start from the beginning. */
|
||||
|
|
@ -201,19 +203,19 @@ static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r
|
|||
}
|
||||
}
|
||||
|
||||
rctx->streamout.begin_emitted = true;
|
||||
sctx->streamout.begin_emitted = true;
|
||||
}
|
||||
|
||||
void si_emit_streamout_end(struct r600_common_context *rctx)
|
||||
void si_emit_streamout_end(struct si_context *sctx)
|
||||
{
|
||||
struct radeon_winsys_cs *cs = rctx->gfx.cs;
|
||||
struct r600_so_target **t = rctx->streamout.targets;
|
||||
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
|
||||
struct si_streamout_target **t = sctx->streamout.targets;
|
||||
unsigned i;
|
||||
uint64_t va;
|
||||
|
||||
r600_flush_vgt_streamout(rctx);
|
||||
si_flush_vgt_streamout(sctx);
|
||||
|
||||
for (i = 0; i < rctx->streamout.num_targets; i++) {
|
||||
for (i = 0; i < sctx->streamout.num_targets; i++) {
|
||||
if (!t[i])
|
||||
continue;
|
||||
|
||||
|
|
@ -227,7 +229,7 @@ void si_emit_streamout_end(struct r600_common_context *rctx)
|
|||
radeon_emit(cs, 0); /* unused */
|
||||
radeon_emit(cs, 0); /* unused */
|
||||
|
||||
r600_emit_reloc(rctx, &rctx->gfx, t[i]->buf_filled_size,
|
||||
r600_emit_reloc(&sctx->b, &sctx->b.gfx, t[i]->buf_filled_size,
|
||||
RADEON_USAGE_WRITE, RADEON_PRIO_SO_FILLED_SIZE);
|
||||
|
||||
/* Zero the buffer size. The counters (primitives generated,
|
||||
|
|
@ -239,8 +241,8 @@ void si_emit_streamout_end(struct r600_common_context *rctx)
|
|||
t[i]->buf_filled_size_valid = true;
|
||||
}
|
||||
|
||||
rctx->streamout.begin_emitted = false;
|
||||
rctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
|
||||
sctx->streamout.begin_emitted = false;
|
||||
sctx->b.flags |= R600_CONTEXT_STREAMOUT_FLUSH;
|
||||
}
|
||||
|
||||
/* STREAMOUT CONFIG DERIVED STATE
|
||||
|
|
@ -250,61 +252,61 @@ void si_emit_streamout_end(struct r600_common_context *rctx)
|
|||
* are no buffers bound.
|
||||
*/
|
||||
|
||||
static void r600_emit_streamout_enable(struct r600_common_context *rctx,
|
||||
struct r600_atom *atom)
|
||||
static void si_emit_streamout_enable(struct r600_common_context *rctx,
|
||||
struct r600_atom *atom)
|
||||
{
|
||||
radeon_set_context_reg_seq(rctx->gfx.cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
|
||||
radeon_emit(rctx->gfx.cs,
|
||||
S_028B94_STREAMOUT_0_EN(r600_get_strmout_en(rctx)) |
|
||||
struct si_context *sctx = (struct si_context*)rctx;
|
||||
|
||||
radeon_set_context_reg_seq(sctx->b.gfx.cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
|
||||
radeon_emit(sctx->b.gfx.cs,
|
||||
S_028B94_STREAMOUT_0_EN(si_get_strmout_en(sctx)) |
|
||||
S_028B94_RAST_STREAM(0) |
|
||||
S_028B94_STREAMOUT_1_EN(r600_get_strmout_en(rctx)) |
|
||||
S_028B94_STREAMOUT_2_EN(r600_get_strmout_en(rctx)) |
|
||||
S_028B94_STREAMOUT_3_EN(r600_get_strmout_en(rctx)));
|
||||
radeon_emit(rctx->gfx.cs,
|
||||
rctx->streamout.hw_enabled_mask &
|
||||
rctx->streamout.enabled_stream_buffers_mask);
|
||||
S_028B94_STREAMOUT_1_EN(si_get_strmout_en(sctx)) |
|
||||
S_028B94_STREAMOUT_2_EN(si_get_strmout_en(sctx)) |
|
||||
S_028B94_STREAMOUT_3_EN(si_get_strmout_en(sctx)));
|
||||
radeon_emit(sctx->b.gfx.cs,
|
||||
sctx->streamout.hw_enabled_mask &
|
||||
sctx->streamout.enabled_stream_buffers_mask);
|
||||
}
|
||||
|
||||
static void r600_set_streamout_enable(struct r600_common_context *rctx, bool enable)
|
||||
static void si_set_streamout_enable(struct si_context *sctx, bool enable)
|
||||
{
|
||||
bool old_strmout_en = r600_get_strmout_en(rctx);
|
||||
unsigned old_hw_enabled_mask = rctx->streamout.hw_enabled_mask;
|
||||
bool old_strmout_en = si_get_strmout_en(sctx);
|
||||
unsigned old_hw_enabled_mask = sctx->streamout.hw_enabled_mask;
|
||||
|
||||
rctx->streamout.streamout_enabled = enable;
|
||||
sctx->streamout.streamout_enabled = enable;
|
||||
|
||||
rctx->streamout.hw_enabled_mask = rctx->streamout.enabled_mask |
|
||||
(rctx->streamout.enabled_mask << 4) |
|
||||
(rctx->streamout.enabled_mask << 8) |
|
||||
(rctx->streamout.enabled_mask << 12);
|
||||
sctx->streamout.hw_enabled_mask = sctx->streamout.enabled_mask |
|
||||
(sctx->streamout.enabled_mask << 4) |
|
||||
(sctx->streamout.enabled_mask << 8) |
|
||||
(sctx->streamout.enabled_mask << 12);
|
||||
|
||||
if ((old_strmout_en != r600_get_strmout_en(rctx)) ||
|
||||
(old_hw_enabled_mask != rctx->streamout.hw_enabled_mask)) {
|
||||
rctx->set_atom_dirty(rctx, &rctx->streamout.enable_atom, true);
|
||||
}
|
||||
if ((old_strmout_en != si_get_strmout_en(sctx)) ||
|
||||
(old_hw_enabled_mask != sctx->streamout.hw_enabled_mask))
|
||||
si_mark_atom_dirty(sctx, &sctx->streamout.enable_atom);
|
||||
}
|
||||
|
||||
void si_update_prims_generated_query_state(struct r600_common_context *rctx,
|
||||
void si_update_prims_generated_query_state(struct si_context *sctx,
|
||||
unsigned type, int diff)
|
||||
{
|
||||
if (type == PIPE_QUERY_PRIMITIVES_GENERATED) {
|
||||
bool old_strmout_en = r600_get_strmout_en(rctx);
|
||||
bool old_strmout_en = si_get_strmout_en(sctx);
|
||||
|
||||
rctx->streamout.num_prims_gen_queries += diff;
|
||||
assert(rctx->streamout.num_prims_gen_queries >= 0);
|
||||
sctx->streamout.num_prims_gen_queries += diff;
|
||||
assert(sctx->streamout.num_prims_gen_queries >= 0);
|
||||
|
||||
rctx->streamout.prims_gen_query_enabled =
|
||||
rctx->streamout.num_prims_gen_queries != 0;
|
||||
sctx->streamout.prims_gen_query_enabled =
|
||||
sctx->streamout.num_prims_gen_queries != 0;
|
||||
|
||||
if (old_strmout_en != r600_get_strmout_en(rctx)) {
|
||||
rctx->set_atom_dirty(rctx, &rctx->streamout.enable_atom, true);
|
||||
}
|
||||
if (old_strmout_en != si_get_strmout_en(sctx))
|
||||
si_mark_atom_dirty(sctx, &sctx->streamout.enable_atom);
|
||||
}
|
||||
}
|
||||
|
||||
void si_streamout_init(struct r600_common_context *rctx)
|
||||
void si_init_streamout_functions(struct si_context *sctx)
|
||||
{
|
||||
rctx->b.create_stream_output_target = r600_create_so_target;
|
||||
rctx->b.stream_output_target_destroy = r600_so_target_destroy;
|
||||
rctx->streamout.begin_atom.emit = r600_emit_streamout_begin;
|
||||
rctx->streamout.enable_atom.emit = r600_emit_streamout_enable;
|
||||
sctx->b.b.create_stream_output_target = si_create_so_target;
|
||||
sctx->b.b.stream_output_target_destroy = si_so_target_destroy;
|
||||
sctx->streamout.begin_atom.emit = si_emit_streamout_begin;
|
||||
sctx->streamout.enable_atom.emit = si_emit_streamout_enable;
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue