fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-20 07:20:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

treewide: use nir_store_global alias of nir_build_store_global

Browse source 
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37959>
This commit is contained in:
Georg Lehmann 2025-10-20 17:27:55 +02:00
parent 2306cba65b
commit 654bd74c60
8 changed files with 56 additions and 62 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
src/amd/vulkan/nir/radv_meta_nir.c
View file

@ -140,7 +140,7 @@ radv_meta_nir_build_fill_memory_shader(struct radv_device *dev, uint32_t bytes_p
nir_def *offset = nir_umin(&b, nir_imul_imm(&b, global_id, bytes_per_invocation), max_offset);
nir_def *dst_addr = nir_iadd(&b, buffer_addr, nir_u2u64(&b, offset));
nir_build_store_global(&b, data, dst_addr, .align_mul = 4);
nir_store_global(&b, data, dst_addr, .align_mul = 4);
return b.shader;
}
@ -169,7 +169,7 @@ radv_meta_nir_build_copy_memory_shader(struct radv_device *dev, uint32_t bytes_p
nir_def *data =
nir_load_global(&b, num_components, bit_size, nir_iadd(&b, src_addr, offset), .align_mul = bit_size / 8);
nir_build_store_global(&b, data, nir_iadd(&b, dst_addr, offset), .align_mul = bit_size / 8);
nir_store_global(&b, data, nir_iadd(&b, dst_addr, offset), .align_mul = bit_size / 8);
return b.shader;
}
@ -892,7 +892,7 @@ radv_meta_nir_build_clear_htile_mask_shader(struct radv_device *dev)
nir_def *data = nir_iand(&b, load, nir_channel(&b, constants, 3));
data = nir_ior(&b, data, nir_channel(&b, constants, 2));
nir_build_store_global(&b, data, va, .access = ACCESS_NON_READABLE, .align_mul = 16);
nir_store_global(&b, data, va, .access = ACCESS_NON_READABLE, .align_mul = 16);
return b.shader;
}
@ -1017,8 +1017,8 @@ radv_meta_nir_build_copy_vrs_htile_shader(struct radv_device *device, struct rad
nir_def *output_value = nir_ior(&b, nir_load_var(&b, htile_value), vrs_rates);
/* Store the updated HTILE 32-bit which contains the VRS rates. */
nir_build_store_global(&b, output_value, nir_iadd(&b, htile_va, nir_u2u64(&b, htile_offset)),
.access = ACCESS_NON_READABLE);
nir_store_global(&b, output_value, nir_iadd(&b, htile_va, nir_u2u64(&b, htile_offset)),
.access = ACCESS_NON_READABLE);
return b.shader;
}

28
src/amd/vulkan/nir/radv_nir_rt_shader.c
View file

@ -907,7 +907,7 @@ radv_build_token_begin(nir_builder *b, struct rt_variables *vars, nir_def *hit,
nir_iadd(b, nir_imul(b, launch_id_comps[1], launch_size_comps[0]),
nir_imul(b, launch_id_comps[2], nir_imul(b, launch_size_comps[0], launch_size_comps[1]))));
nir_def *launch_index_and_hit = nir_bcsel(b, hit, nir_ior_imm(b, global_index, 1u << 29u), global_index);
nir_build_store_global(b, nir_ior_imm(b, launch_index_and_hit, token_type << 30), dst_addr, .align_mul = 4);
nir_store_global(b, nir_ior_imm(b, launch_index_and_hit, token_type << 30), dst_addr, .align_mul = 4);
return nir_iadd_imm(b, dst_addr, 4);
}
@ -929,7 +929,7 @@ radv_build_end_trace_token(nir_builder *b, struct rt_variables *vars, nir_def *t
nir_def *dst_addr = radv_build_token_begin(b, vars, hit, radv_packed_token_end_trace, token_size,
sizeof(struct radv_packed_end_trace_token));
{
nir_build_store_global(b, nir_load_var(b, vars->accel_struct), dst_addr, .align_mul = 4);
nir_store_global(b, nir_load_var(b, vars->accel_struct), dst_addr, .align_mul = 4);
dst_addr = nir_iadd_imm(b, dst_addr, 8);
nir_def *dispatch_indices =
@ -938,7 +938,7 @@ radv_build_end_trace_token(nir_builder *b, struct rt_variables *vars, nir_def *t
nir_def *dispatch_index = nir_iadd(b, nir_channel(b, dispatch_indices, 0), nir_channel(b, dispatch_indices, 1));
nir_def *dispatch_and_flags = nir_iand_imm(b, nir_load_var(b, vars->cull_mask_and_flags), 0xFFFF);
dispatch_and_flags = nir_ior(b, dispatch_and_flags, dispatch_index);
nir_build_store_global(b, dispatch_and_flags, dst_addr, .align_mul = 4);
nir_store_global(b, dispatch_and_flags, dst_addr, .align_mul = 4);
dst_addr = nir_iadd_imm(b, dst_addr, 4);
nir_def *shifted_cull_mask = nir_iand_imm(b, nir_load_var(b, vars->cull_mask_and_flags), 0xFF000000);
@ -947,34 +947,34 @@ radv_build_end_trace_token(nir_builder *b, struct rt_variables *vars, nir_def *t
packed_args = nir_ior(b, packed_args, nir_ishl_imm(b, nir_load_var(b, vars->sbt_stride), 4));
packed_args = nir_ior(b, packed_args, nir_ishl_imm(b, nir_load_var(b, vars->miss_index), 8));
packed_args = nir_ior(b, packed_args, shifted_cull_mask);
nir_build_store_global(b, packed_args, dst_addr, .align_mul = 4);
nir_store_global(b, packed_args, dst_addr, .align_mul = 4);
dst_addr = nir_iadd_imm(b, dst_addr, 4);
nir_build_store_global(b, nir_load_var(b, vars->origin), dst_addr, .align_mul = 4);
nir_store_global(b, nir_load_var(b, vars->origin), dst_addr, .align_mul = 4);
dst_addr = nir_iadd_imm(b, dst_addr, 12);
nir_build_store_global(b, nir_load_var(b, vars->tmin), dst_addr, .align_mul = 4);
nir_store_global(b, nir_load_var(b, vars->tmin), dst_addr, .align_mul = 4);
dst_addr = nir_iadd_imm(b, dst_addr, 4);
nir_build_store_global(b, nir_load_var(b, vars->direction), dst_addr, .align_mul = 4);
nir_store_global(b, nir_load_var(b, vars->direction), dst_addr, .align_mul = 4);
dst_addr = nir_iadd_imm(b, dst_addr, 12);
nir_build_store_global(b, tmax, dst_addr, .align_mul = 4);
nir_store_global(b, tmax, dst_addr, .align_mul = 4);
dst_addr = nir_iadd_imm(b, dst_addr, 4);
nir_build_store_global(b, iteration_instance_count, dst_addr, .align_mul = 4);
nir_store_global(b, iteration_instance_count, dst_addr, .align_mul = 4);
dst_addr = nir_iadd_imm(b, dst_addr, 4);
nir_build_store_global(b, nir_load_var(b, vars->ahit_isec_count), dst_addr, .align_mul = 4);
nir_store_global(b, nir_load_var(b, vars->ahit_isec_count), dst_addr, .align_mul = 4);
dst_addr = nir_iadd_imm(b, dst_addr, 4);
nir_push_if(b, hit);
{
nir_build_store_global(b, nir_load_var(b, vars->primitive_id), dst_addr, .align_mul = 4);
nir_store_global(b, nir_load_var(b, vars->primitive_id), dst_addr, .align_mul = 4);
dst_addr = nir_iadd_imm(b, dst_addr, 4);
nir_def *geometry_id = nir_iand_imm(b, nir_load_var(b, vars->geometry_id_and_flags), 0xFFFFFFF);
nir_build_store_global(b, geometry_id, dst_addr, .align_mul = 4);
nir_store_global(b, geometry_id, dst_addr, .align_mul = 4);
dst_addr = nir_iadd_imm(b, dst_addr, 4);
nir_def *instance_id_and_hit_kind =
@ -983,10 +983,10 @@ radv_build_end_trace_token(nir_builder *b, struct rt_variables *vars, nir_def *t
offsetof(struct radv_bvh_instance_node, instance_id)));
instance_id_and_hit_kind =
nir_ior(b, instance_id_and_hit_kind, nir_ishl_imm(b, nir_load_var(b, vars->hit_kind), 24));
nir_build_store_global(b, instance_id_and_hit_kind, dst_addr, .align_mul = 4);
nir_store_global(b, instance_id_and_hit_kind, dst_addr, .align_mul = 4);
dst_addr = nir_iadd_imm(b, dst_addr, 4);
nir_build_store_global(b, nir_load_var(b, vars->tmax), dst_addr, .align_mul = 4);
nir_store_global(b, nir_load_var(b, vars->tmax), dst_addr, .align_mul = 4);
dst_addr = nir_iadd_imm(b, dst_addr, 4);
}
nir_pop_if(b, NULL);

15
src/amd/vulkan/radv_dgc.c
View file

@ -797,7 +797,7 @@ dgc_emit(struct dgc_cmdbuf *cs, unsigned count, nir_def **values)
nir_def *offset = nir_load_var(b, cs->offset);
nir_def *store_val = nir_vec(b, values + i, MIN2(count - i, 4));
assert(store_val->bit_size >= 32);
nir_build_store_global(b, store_val, nir_iadd(b, cs->va, nir_u2u64(b, offset)), .access = ACCESS_NON_READABLE);
nir_store_global(b, store_val, nir_iadd(b, cs->va, nir_u2u64(b, offset)), .access = ACCESS_NON_READABLE);
nir_store_var(b, cs->offset, nir_iadd_imm(b, offset, store_val->num_components * store_val->bit_size / 8), 0x1);
}
}
@ -808,7 +808,7 @@ dgc_upload(struct dgc_cmdbuf *cs, nir_def *data)
nir_builder *b = cs->b;
nir_def *upload_offset = nir_load_var(b, cs->upload_offset);
nir_build_store_global(b, data, nir_iadd(b, cs->va, nir_u2u64(b, upload_offset)), .access = ACCESS_NON_READABLE);
nir_store_global(b, data, nir_iadd(b, cs->va, nir_u2u64(b, upload_offset)), .access = ACCESS_NON_READABLE);
nir_store_var(b, cs->upload_offset, nir_iadd_imm(b, upload_offset, data->num_components * data->bit_size / 8), 0x1);
}
@ -1019,7 +1019,7 @@ dgc_emit_indirect_buffer(struct dgc_cmdbuf *cs, nir_def *va, nir_def *ib_offset,
nir_ior_imm(b, ib_cdw, S_3F2_CHAIN(1) | S_3F2_VALID(1) | S_3F2_PRE_ENA(false)),
};
nir_build_store_global(b, nir_vec(b, packet, 4), va, .access = ACCESS_NON_READABLE);
nir_store_global(b, nir_vec(b, packet, 4), va, .access = ACCESS_NON_READABLE);
}
static void
@ -1046,7 +1046,7 @@ dgc_emit_padding(struct dgc_cmdbuf *cs, nir_def *cmd_buf_offset, nir_def *size)
len = nir_iadd_imm(b, len, -2);
nir_def *packet = nir_pkt3(b, PKT3_NOP, len);
nir_build_store_global(b, packet, nir_iadd(b, va, nir_u2u64(b, curr_offset)), .access = ACCESS_NON_READABLE);
nir_store_global(b, packet, nir_iadd(b, va, nir_u2u64(b, curr_offset)), .access = ACCESS_NON_READABLE);
nir_store_var(b, offset, nir_iadd(b, curr_offset, packet_size), 0x1);
}
@ -1159,8 +1159,7 @@ build_dgc_buffer_trailer(struct dgc_cmdbuf *cs, nir_def *cmd_buf_offset, unsigne
nir_imm_int(b, PKT3_NOP_PAD),
};
nir_build_store_global(b, nir_vec(b, nop_packets, 4), nir_iadd_imm(b, va, pad_size),
.access = ACCESS_NON_READABLE);
nir_store_global(b, nir_vec(b, nop_packets, 4), nir_iadd_imm(b, va, pad_size), .access = ACCESS_NON_READABLE);
}
nir_pop_if(b, NULL);
}
@ -1758,7 +1757,7 @@ dgc_alloc_push_constant(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_def *se
nir_def *data = nir_load_global(b, 1, 32, nir_iadd(b, va, nir_u2u64(b, pc_offset)));
nir_def *offset = nir_iadd(b, upload_offset_pc, nir_imul_imm(b, cur_idx, 4));
nir_build_store_global(b, data, nir_iadd(b, cs->va, nir_u2u64(b, offset)), .access = ACCESS_NON_READABLE);
nir_store_global(b, data, nir_iadd(b, cs->va, nir_u2u64(b, offset)), .access = ACCESS_NON_READABLE);
nir_store_var(b, idx, nir_iadd_imm(b, cur_idx, 1), 0x1);
}
@ -1776,7 +1775,7 @@ dgc_alloc_push_constant(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_def *se
}
nir_def *offset = nir_iadd_imm(b, upload_offset_pc, i * 4);
nir_build_store_global(b, data, nir_iadd(b, cs->va, nir_u2u64(b, offset)), .access = ACCESS_NON_READABLE);
nir_store_global(b, data, nir_iadd(b, cs->va, nir_u2u64(b, offset)), .access = ACCESS_NON_READABLE);
}
nir_def *pc_size = nir_imul_imm(b, load_param8(b, push_constant_size), 4);

45
src/amd/vulkan/radv_query.c
View file

@ -132,12 +132,12 @@ radv_store_availability(nir_builder *b, nir_def *flags, nir_def *dst_va, nir_def
nir_push_if(b, nir_test_mask(b, flags, VK_QUERY_RESULT_64_BIT));
nir_build_store_global(b, nir_vec2(b, value32, nir_imm_int(b, 0)), nir_iadd(b, dst_va, nir_u2u64(b, offset)),
.align_mul = 8);
nir_store_global(b, nir_vec2(b, value32, nir_imm_int(b, 0)), nir_iadd(b, dst_va, nir_u2u64(b, offset)),
.align_mul = 8);
nir_push_else(b, NULL);
nir_build_store_global(b, value32, nir_iadd(b, dst_va, nir_u2u64(b, offset)));
nir_store_global(b, value32, nir_iadd(b, dst_va, nir_u2u64(b, offset)));
nir_pop_if(b, NULL);
@ -293,13 +293,12 @@ build_occlusion_query_shader(struct radv_device *device)
nir_push_if(&b, result_is_64bit);
nir_build_store_global(&b, nir_load_var(&b, result), nir_iadd(&b, dst_va, nir_u2u64(&b, output_base)),
.align_mul = 8);
nir_store_global(&b, nir_load_var(&b, result), nir_iadd(&b, dst_va, nir_u2u64(&b, output_base)), .align_mul = 8);
nir_push_else(&b, NULL);
nir_build_store_global(&b, nir_u2u32(&b, nir_load_var(&b, result)), nir_iadd(&b, dst_va, nir_u2u64(&b, output_base)),
.align_mul = 8);
nir_store_global(&b, nir_u2u32(&b, nir_load_var(&b, result)), nir_iadd(&b, dst_va, nir_u2u64(&b, output_base)),
.align_mul = 8);
nir_pop_if(&b, NULL);
nir_pop_if(&b, NULL);
@ -558,13 +557,13 @@ build_pipeline_statistics_query_shader(struct radv_device *device)
/* Store result */
nir_push_if(&b, result_is_64bit);
nir_build_store_global(&b, nir_load_var(&b, result),
nir_iadd(&b, dst_va, nir_u2u64(&b, nir_load_var(&b, output_offset))));
nir_store_global(&b, nir_load_var(&b, result),
nir_iadd(&b, dst_va, nir_u2u64(&b, nir_load_var(&b, output_offset))));
nir_push_else(&b, NULL);
nir_build_store_global(&b, nir_u2u32(&b, nir_load_var(&b, result)),
nir_iadd(&b, dst_va, nir_u2u64(&b, nir_load_var(&b, output_offset))));
nir_store_global(&b, nir_u2u32(&b, nir_load_var(&b, result)),
nir_iadd(&b, dst_va, nir_u2u64(&b, nir_load_var(&b, output_offset))));
nir_pop_if(&b, NULL);
@ -590,11 +589,11 @@ build_pipeline_statistics_query_shader(struct radv_device *device)
nir_def *output_elem = nir_iadd(&b, output_base, nir_imul(&b, elem_size, current_counter));
nir_push_if(&b, result_is_64bit);
nir_build_store_global(&b, nir_imm_int64(&b, 0), nir_iadd(&b, dst_va, nir_u2u64(&b, output_elem)));
nir_store_global(&b, nir_imm_int64(&b, 0), nir_iadd(&b, dst_va, nir_u2u64(&b, output_elem)));
nir_push_else(&b, NULL);
nir_build_store_global(&b, nir_imm_int(&b, 0), nir_iadd(&b, dst_va, nir_u2u64(&b, output_elem)));
nir_store_global(&b, nir_imm_int(&b, 0), nir_iadd(&b, dst_va, nir_u2u64(&b, output_elem)));
nir_pop_if(&b, NULL);
@ -916,12 +915,11 @@ build_tfb_query_shader(struct radv_device *device)
/* Store result. */
nir_push_if(&b, result_is_64bit);
nir_build_store_global(&b, nir_load_var(&b, result), nir_iadd(&b, dst_va, nir_u2u64(&b, output_base)));
nir_store_global(&b, nir_load_var(&b, result), nir_iadd(&b, dst_va, nir_u2u64(&b, output_base)));
nir_push_else(&b, NULL);
nir_build_store_global(&b, nir_u2u32(&b, nir_load_var(&b, result)),
nir_iadd(&b, dst_va, nir_u2u64(&b, output_base)));
nir_store_global(&b, nir_u2u32(&b, nir_load_var(&b, result)), nir_iadd(&b, dst_va, nir_u2u64(&b, output_base)));
nir_pop_if(&b, NULL);
nir_pop_if(&b, NULL);
@ -1142,12 +1140,11 @@ build_timestamp_query_shader(struct radv_device *device)
/* Store result. */
nir_push_if(&b, result_is_64bit);
nir_build_store_global(&b, nir_load_var(&b, result), nir_iadd(&b, dst_va, nir_u2u64(&b, output_base)));
nir_store_global(&b, nir_load_var(&b, result), nir_iadd(&b, dst_va, nir_u2u64(&b, output_base)));
nir_push_else(&b, NULL);
nir_build_store_global(&b, nir_u2u32(&b, nir_load_var(&b, result)),
nir_iadd(&b, dst_va, nir_u2u64(&b, output_base)));
nir_store_global(&b, nir_u2u32(&b, nir_load_var(&b, result)), nir_iadd(&b, dst_va, nir_u2u64(&b, output_base)));
nir_pop_if(&b, NULL);
@ -1323,12 +1320,11 @@ build_pg_query_shader(struct radv_device *device)
/* Store result. */
nir_push_if(&b, result_is_64bit);
nir_build_store_global(&b, nir_load_var(&b, result), nir_iadd(&b, dst_va, nir_u2u64(&b, output_base)));
nir_store_global(&b, nir_load_var(&b, result), nir_iadd(&b, dst_va, nir_u2u64(&b, output_base)));
nir_push_else(&b, NULL);
nir_build_store_global(&b, nir_u2u32(&b, nir_load_var(&b, result)),
nir_iadd(&b, dst_va, nir_u2u64(&b, output_base)));
nir_store_global(&b, nir_u2u32(&b, nir_load_var(&b, result)), nir_iadd(&b, dst_va, nir_u2u64(&b, output_base)));
nir_pop_if(&b, NULL);
nir_pop_if(&b, NULL);
@ -1568,12 +1564,11 @@ build_ms_prim_gen_query_shader(struct radv_device *device)
/* Store result. */
nir_push_if(&b, result_is_64bit);
nir_build_store_global(&b, nir_load_var(&b, result), nir_iadd(&b, dst_va, nir_u2u64(&b, output_base)));
nir_store_global(&b, nir_load_var(&b, result), nir_iadd(&b, dst_va, nir_u2u64(&b, output_base)));
nir_push_else(&b, NULL);
nir_build_store_global(&b, nir_u2u32(&b, nir_load_var(&b, result)),
nir_iadd(&b, dst_va, nir_u2u64(&b, output_base)));
nir_store_global(&b, nir_u2u32(&b, nir_load_var(&b, result)), nir_iadd(&b, dst_va, nir_u2u64(&b, output_base)));
nir_pop_if(&b, NULL);
nir_pop_if(&b, NULL);

10
src/compiler/nir/nir_lower_ssbo.c
View file

@ -50,11 +50,11 @@ pass(nir_builder *b, nir_intrinsic_instr *intr, void *data)
break;
case nir_intrinsic_store_ssbo:
nir_build_store_global(b, intr->src[0].ssa,
calc_address(b, intr, opts),
.align_mul = nir_intrinsic_align_mul(intr),
.align_offset = nir_intrinsic_align_offset(intr),
.write_mask = nir_intrinsic_write_mask(intr));
nir_store_global(b, intr->src[0].ssa,
calc_address(b, intr, opts),
.align_mul = nir_intrinsic_align_mul(intr),
.align_offset = nir_intrinsic_align_offset(intr),
.write_mask = nir_intrinsic_write_mask(intr));
break;
case nir_intrinsic_ssbo_atomic:

4
src/compiler/nir/nir_opt_intrinsics.c
View file

@ -418,8 +418,8 @@ try_opt_atomic_exchange_to_store(nir_builder *b, nir_intrinsic_instr *intrin)
.base = nir_intrinsic_base(intrin));
break;
case nir_intrinsic_global_atomic:
nir_build_store_global(b, intrin->src[1].ssa, intrin->src[0].ssa,
.access = ACCESS_ATOMIC | ACCESS_COHERENT);
nir_store_global(b, intrin->src[1].ssa, intrin->src[0].ssa,
.access = ACCESS_ATOMIC | ACCESS_COHERENT);
break;
case nir_intrinsic_global_atomic_amd:
nir_store_global_amd(b, intrin->src[1].ssa, intrin->src[0].ssa, intrin->src[2].ssa,

2
src/intel/compiler/brw/brw_nir_rt_builder.h
View file

@ -52,7 +52,7 @@ static inline void
brw_nir_rt_store(nir_builder *b, nir_def *addr, unsigned align,
nir_def *value, unsigned write_mask)
{
nir_build_store_global(b, value, addr,
nir_store_global(b, value, addr,
.align_mul = align,
.write_mask = (write_mask) &
BITFIELD_MASK(value->num_components),

4
src/vulkan/runtime/vk_meta_copy_fill_update.c
View file

@ -2373,7 +2373,7 @@ build_copy_buffer_shader(const struct vk_meta_device *meta,
nir_iadd(b, src_addr, offset),
.align_mul = chunk_bit_size / 8);
nir_build_store_global(b, data, nir_iadd(b, dst_addr, offset),
nir_store_global(b, data, nir_iadd(b, dst_addr, offset),
.align_mul = key->chunk_size);
nir_pop_if(b, NULL);
@ -2552,7 +2552,7 @@ build_fill_buffer_shader(const struct vk_meta_device *meta,
nir_def *buf_addr =
load_info(b, struct vk_meta_fill_buffer_info, buf_addr);
nir_build_store_global(b, data, nir_iadd(b, buf_addr, offset),
nir_store_global(b, data, nir_iadd(b, buf_addr, offset),
.align_mul = 4);
nir_pop_if(b, NULL);