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pan/bi: Rework indices for attributes on Valhall
This also fix missing encoding of indice with non immediate index. Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27846>
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27031910f7
commit
652e1c2e13
4 changed files with 107 additions and 32 deletions
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@ -74,13 +74,38 @@ lower_image_intrin(nir_builder *b, nir_intrinsic_instr *intrin)
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}
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static bool
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lower_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin)
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lower_input_intrin(nir_builder *b, nir_intrinsic_instr *intrin,
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const struct panfrost_compile_inputs *inputs)
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{
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/* We always use heap-based varying allocation when IDVS is used on Valhall. */
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bool malloc_idvs = !inputs->no_idvs;
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/* All vertex attributes come from the attribute table.
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* Fragment inputs come from the attribute table too, unless they've
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* been allocated on the heap.
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*/
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if (b->shader->info.stage == MESA_SHADER_VERTEX ||
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(b->shader->info.stage == MESA_SHADER_FRAGMENT && !malloc_idvs)) {
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nir_intrinsic_set_base(
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intrin,
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pan_res_handle(PAN_TABLE_ATTRIBUTE, nir_intrinsic_base(intrin)));
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return true;
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}
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return false;
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}
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static bool
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lower_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin,
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const struct panfrost_compile_inputs *inputs)
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{
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switch (intrin->intrinsic) {
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case nir_intrinsic_image_load:
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case nir_intrinsic_image_store:
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case nir_intrinsic_image_texel_address:
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return lower_image_intrin(b, intrin);
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case nir_intrinsic_load_input:
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return lower_input_intrin(b, intrin, inputs);
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default:
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return false;
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}
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@ -89,11 +114,13 @@ lower_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin)
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static bool
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lower_instr(nir_builder *b, nir_instr *instr, void *data)
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{
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const struct panfrost_compile_inputs *inputs = data;
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switch (instr->type) {
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case nir_instr_type_tex:
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return lower_tex(b, nir_instr_as_tex(instr));
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case nir_instr_type_intrinsic:
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return lower_intrinsic(b, nir_instr_as_intrinsic(instr));
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return lower_intrinsic(b, nir_instr_as_intrinsic(instr), inputs);
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default:
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return false;
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}
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@ -390,6 +390,40 @@ bi_is_intr_immediate(nir_intrinsic_instr *instr, unsigned *immediate,
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return (*immediate) < max;
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}
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static bool
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bi_is_imm_desc_handle(bi_builder *b, nir_intrinsic_instr *instr,
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uint32_t *immediate, unsigned max)
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{
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nir_src *offset = nir_get_io_offset_src(instr);
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if (!nir_src_is_const(*offset))
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return false;
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if (b->shader->arch >= 9) {
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uint32_t res_handle =
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nir_intrinsic_base(instr) + nir_src_as_uint(*offset);
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uint32_t table_index = pan_res_handle_get_table(res_handle);
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uint32_t res_index = pan_res_handle_get_index(res_handle);
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if (!va_is_valid_const_table(table_index) || res_index >= max)
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return false;
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*immediate = res_handle;
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return true;
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}
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return bi_is_intr_immediate(instr, immediate, max);
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}
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static bool
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bi_is_imm_var_desc_handle(bi_builder *b, nir_intrinsic_instr *instr,
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uint32_t *immediate)
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{
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unsigned max = b->shader->arch >= 9 ? 256 : 20;
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return bi_is_imm_desc_handle(b, instr, immediate, max);
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}
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static void bi_make_vec_to(bi_builder *b, bi_index final_dst, bi_index *src,
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unsigned *channel, unsigned count, unsigned bitsize);
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@ -439,14 +473,17 @@ bi_emit_load_attr(bi_builder *b, nir_intrinsic_instr *instr)
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unsigned imm_index = 0;
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unsigned base = nir_intrinsic_base(instr);
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bool constant = nir_src_is_const(*offset);
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bool immediate = bi_is_intr_immediate(instr, &imm_index, 16);
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bool immediate = bi_is_imm_desc_handle(b, instr, &imm_index, 16);
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bi_index dest =
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(component == 0) ? bi_def_index(&instr->def) : bi_temp(b->shader);
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bi_instr *I;
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if (immediate) {
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I = bi_ld_attr_imm_to(b, dest, bi_vertex_id(b), bi_instance_id(b), regfmt,
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vecsize, imm_index);
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vecsize, pan_res_handle_get_index(imm_index));
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if (b->shader->arch >= 9)
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I->table = va_res_fold_table_idx(pan_res_handle_get_table(base));
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} else {
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bi_index idx = bi_src_index(&instr->src[0]);
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@ -459,9 +496,6 @@ bi_emit_load_attr(bi_builder *b, nir_intrinsic_instr *instr)
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regfmt, vecsize);
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}
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if (b->shader->arch >= 9)
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I->table = PAN_TABLE_ATTRIBUTE;
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bi_copy_component(b, instr, dest);
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}
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@ -544,23 +578,38 @@ bi_emit_load_vary(bi_builder *b, nir_intrinsic_instr *instr)
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nir_src *offset = nir_get_io_offset_src(instr);
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unsigned imm_index = 0;
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bool immediate = bi_is_intr_immediate(instr, &imm_index, 20);
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bi_instr *I = NULL;
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bool immediate = bi_is_imm_var_desc_handle(b, instr, &imm_index);
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unsigned base = nir_intrinsic_base(instr);
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/* On Valhall, ensure the table and index are valid for usage with immediate
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* form when IDVS isn't used */
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if (b->shader->arch >= 9 && !b->shader->malloc_idvs)
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immediate &= va_is_valid_const_table(pan_res_handle_get_table(base)) &&
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pan_res_handle_get_index(base) < 256;
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if (b->shader->malloc_idvs && immediate) {
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/* Immediate index given in bytes. */
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bi_ld_var_buf_imm_to(b, sz, dest, src0, regfmt, sample, source_format,
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update, vecsize,
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bi_varying_offset(b->shader, instr));
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} else if (immediate && smooth) {
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} else if (immediate) {
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bi_instr *I;
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if (smooth) {
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I = bi_ld_var_imm_to(b, dest, src0, regfmt, sample, update, vecsize,
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imm_index);
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} else if (immediate && !smooth) {
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pan_res_handle_get_index(imm_index));
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} else {
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I = bi_ld_var_flat_imm_to(b, dest, BI_FUNCTION_NONE, regfmt, vecsize,
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imm_index);
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pan_res_handle_get_index(imm_index));
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}
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/* Valhall usually uses machine-allocated IDVS. If this is disabled,
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* use a simple Midgard-style ABI.
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*/
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if (b->shader->arch >= 9)
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I->table = va_res_fold_table_idx(pan_res_handle_get_table(base));
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} else {
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bi_index idx = bi_src_index(offset);
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unsigned base = nir_intrinsic_base(instr);
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if (b->shader->malloc_idvs) {
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/* Index needs to be in bytes, but NIR gives the index
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@ -574,25 +623,17 @@ bi_emit_load_vary(bi_builder *b, nir_intrinsic_instr *instr)
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bi_ld_var_buf_to(b, sz, dest, src0, idx_bytes, regfmt, sample,
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source_format, update, vecsize);
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} else if (smooth) {
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if (base != 0)
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idx = bi_iadd_u32(b, idx, bi_imm_u32(base), false);
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I = bi_ld_var_to(b, dest, src0, idx, regfmt, sample, update, vecsize);
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} else {
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if (base != 0)
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idx = bi_iadd_u32(b, idx, bi_imm_u32(base), false);
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I = bi_ld_var_flat_to(b, dest, idx, BI_FUNCTION_NONE, regfmt, vecsize);
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if (smooth)
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bi_ld_var_to(b, dest, src0, idx, regfmt, sample, update, vecsize);
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else
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bi_ld_var_flat_to(b, dest, idx, BI_FUNCTION_NONE, regfmt, vecsize);
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}
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}
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/* Valhall usually uses machine-allocated IDVS. If this is disabled, use
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* a simple Midgard-style ABI.
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*/
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if (b->shader->arch >= 9 && I != NULL)
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I->table = PAN_TABLE_ATTRIBUTE;
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bi_copy_component(b, instr, dest);
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}
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@ -414,6 +414,12 @@ tex_hw_index(uint32_t index)
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return PAN_ARCH >= 9 ? pan_res_handle(PAN_TABLE_TEXTURE, index) : index;
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}
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static uint32_t
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attr_hw_index(uint32_t index)
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{
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return PAN_ARCH >= 9 ? pan_res_handle(PAN_TABLE_ATTRIBUTE, index) : index;
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}
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static const struct pan_blit_shader_data *
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pan_blitter_get_blit_shader(struct pan_blitter_cache *cache,
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const struct pan_blit_shader_key *key)
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@ -484,12 +490,13 @@ pan_blitter_get_blit_shader(struct pan_blitter_cache *cache,
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nir_builder b = nir_builder_init_simple_shader(
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MESA_SHADER_FRAGMENT, GENX(pan_shader_get_compiler_options)(),
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"pan_blit(%s)", sig);
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nir_def *barycentric = nir_load_barycentric(
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&b, nir_intrinsic_load_barycentric_pixel, INTERP_MODE_SMOOTH);
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nir_def *coord = nir_load_interpolated_input(
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&b, coord_comps, 32, barycentric, nir_imm_int(&b, 0), .base = 0,
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.dest_type = nir_type_float32, .io_semantics.location = VARYING_SLOT_VAR0,
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.io_semantics.num_slots = 1);
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&b, coord_comps, 32, barycentric, nir_imm_int(&b, 0),
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.base = attr_hw_index(0), .dest_type = nir_type_float32,
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.io_semantics.location = VARYING_SLOT_VAR0, .io_semantics.num_slots = 1);
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unsigned active_count = 0;
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for (unsigned i = 0; i < ARRAY_SIZE(key->surfaces); i++) {
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@ -137,7 +137,7 @@ walk_varyings(UNUSED nir_builder *b, nir_instr *instr, void *data)
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/* Consider each slot separately */
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for (unsigned offset = 0; offset < sem.num_slots; ++offset) {
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unsigned location = sem.location + offset;
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unsigned index = nir_intrinsic_base(intr) + offset;
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unsigned index = pan_res_handle_get_index(nir_intrinsic_base(intr)) + offset;
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if (slots[location].type) {
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assert(slots[location].type == type);
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