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Clear optimizations.

Browse source 
- Correct comparison of stencil writemask with 0xff.
	- Do depth with triangles if we are already doing stencil that way.
This commit is contained in:
Keith Whitwell 2006-03-13 18:53:01 +00:00
parent 9f2b49a7b3
commit 651985f813
10 changed files with 126 additions and 51 deletions
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44
src/mesa/drivers/dri/i915/i830_metaops.c
View file

@ -57,7 +57,7 @@ do { \
} while (0)
static void set_no_depth_stencil_write( struct intel_context *intel )
static void set_no_stencil_write( struct intel_context *intel )
{
struct i830_context *i830 = i830_context(&intel->ctx);
@ -68,6 +68,12 @@ static void set_no_depth_stencil_write( struct intel_context *intel )
i830->meta.Ctx[I830_CTXREG_ENABLES_1] |= DISABLE_STENCIL_TEST;
i830->meta.Ctx[I830_CTXREG_ENABLES_2] |= DISABLE_STENCIL_WRITE;
i830->meta.emitted &= ~I830_UPLOAD_CTX;
}
static void set_no_depth_write( struct intel_context *intel )
{
struct i830_context *i830 = i830_context(&intel->ctx);
/* ctx->Driver.Enable( ctx, GL_DEPTH_TEST, GL_FALSE )
*/
@ -79,6 +85,30 @@ static void set_no_depth_stencil_write( struct intel_context *intel )
i830->meta.emitted &= ~I830_UPLOAD_CTX;
}
/* Set depth unit to replace.
*/
static void set_depth_replace( struct intel_context *intel )
{
struct i830_context *i830 = i830_context(&intel->ctx);
/* ctx->Driver.Enable( ctx, GL_DEPTH_TEST, GL_FALSE )
* ctx->Driver.DepthMask( ctx, GL_TRUE )
*/
i830->meta.Ctx[I830_CTXREG_ENABLES_1] &= ~ENABLE_DIS_DEPTH_TEST_MASK;
i830->meta.Ctx[I830_CTXREG_ENABLES_2] &= ~ENABLE_DIS_DEPTH_WRITE_MASK;
i830->meta.Ctx[I830_CTXREG_ENABLES_1] |= ENABLE_DEPTH_TEST;
i830->meta.Ctx[I830_CTXREG_ENABLES_2] |= ENABLE_DEPTH_WRITE;
/* ctx->Driver.DepthFunc( ctx, GL_ALWAYS )
*/
i830->meta.Ctx[I830_CTXREG_STATE3] &= ~DEPTH_TEST_FUNC_MASK;
i830->meta.Ctx[I830_CTXREG_STATE3] |= (ENABLE_DEPTH_TEST_FUNC |
DEPTH_TEST_FUNC(COMPAREFUNC_ALWAYS));
i830->meta.emitted &= ~I830_UPLOAD_CTX;
}
/* Set stencil unit to replace always with the reference value.
*/
static void set_stencil_replace( struct intel_context *intel,
@ -92,14 +122,6 @@ static void set_stencil_replace( struct intel_context *intel,
i830->meta.Ctx[I830_CTXREG_ENABLES_1] |= ENABLE_STENCIL_TEST;
i830->meta.Ctx[I830_CTXREG_ENABLES_2] |= ENABLE_STENCIL_WRITE;
/* ctx->Driver.Enable( ctx, GL_DEPTH_TEST, GL_FALSE )
*/
i830->meta.Ctx[I830_CTXREG_ENABLES_1] &= ~ENABLE_DIS_DEPTH_TEST_MASK;
i830->meta.Ctx[I830_CTXREG_ENABLES_2] &= ~ENABLE_DIS_DEPTH_WRITE_MASK;
i830->meta.Ctx[I830_CTXREG_ENABLES_1] |= DISABLE_DEPTH_TEST;
i830->meta.Ctx[I830_CTXREG_ENABLES_2] |= DISABLE_DEPTH_WRITE;
/* ctx->Driver.StencilMask( ctx, s_mask )
*/
i830->meta.Ctx[I830_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_WRITE_MASK;
@ -427,8 +449,10 @@ void i830InitMetaFuncs( struct i830_context *i830 )
{
i830->intel.vtbl.install_meta_state = install_meta_state;
i830->intel.vtbl.leave_meta_state = leave_meta_state;
i830->intel.vtbl.meta_no_depth_stencil_write = set_no_depth_stencil_write;
i830->intel.vtbl.meta_no_depth_write = set_no_depth_write;
i830->intel.vtbl.meta_no_stencil_write = set_no_stencil_write;
i830->intel.vtbl.meta_stencil_replace = set_stencil_replace;
i830->intel.vtbl.meta_depth_replace = set_depth_replace;
i830->intel.vtbl.meta_color_mask = set_color_mask;
i830->intel.vtbl.meta_no_texture = set_no_texture;
i830->intel.vtbl.meta_texture_blend_replace = set_texture_blend_replace;

39
src/mesa/drivers/dri/i915/i915_metaops.c
View file

@ -57,7 +57,7 @@ do { \
} while (0)
static void meta_no_depth_stencil_write( struct intel_context *intel )
static void meta_no_stencil_write( struct intel_context *intel )
{
struct i915_context *i915 = i915_context(&intel->ctx);
@ -66,6 +66,13 @@ static void meta_no_depth_stencil_write( struct intel_context *intel )
i915->meta.Ctx[I915_CTXREG_LIS5] &= ~(S5_STENCIL_TEST_ENABLE |
S5_STENCIL_WRITE_ENABLE);
i915->meta.emitted &= ~I915_UPLOAD_CTX;
}
static void meta_no_depth_write( struct intel_context *intel )
{
struct i915_context *i915 = i915_context(&intel->ctx);
/* ctx->Driver.Enable( ctx, GL_DEPTH_TEST, GL_FALSE )
*/
i915->meta.Ctx[I915_CTXREG_LIS6] &= ~(S6_DEPTH_TEST_ENABLE |
@ -74,6 +81,26 @@ static void meta_no_depth_stencil_write( struct intel_context *intel )
i915->meta.emitted &= ~I915_UPLOAD_CTX;
}
static void meta_depth_replace( struct intel_context *intel )
{
struct i915_context *i915 = i915_context(&intel->ctx);
/* ctx->Driver.Enable( ctx, GL_DEPTH_TEST, GL_TRUE )
* ctx->Driver.DepthMask( ctx, GL_TRUE )
*/
i915->meta.Ctx[I915_CTXREG_LIS6] |= (S6_DEPTH_TEST_ENABLE |
S6_DEPTH_WRITE_ENABLE);
/* ctx->Driver.DepthFunc( ctx, GL_REPLACE )
*/
i915->meta.Ctx[I915_CTXREG_LIS6] &= ~S6_DEPTH_TEST_FUNC_MASK;
i915->meta.Ctx[I915_CTXREG_LIS6] |=
COMPAREFUNC_ALWAYS << S6_DEPTH_TEST_FUNC_SHIFT;
i915->meta.emitted &= ~I915_UPLOAD_CTX;
}
/* Set stencil unit to replace always with the reference value.
*/
static void meta_stencil_replace( struct intel_context *intel,
@ -89,12 +116,6 @@ static void meta_stencil_replace( struct intel_context *intel,
i915->meta.Ctx[I915_CTXREG_LIS5] |= (S5_STENCIL_TEST_ENABLE |
S5_STENCIL_WRITE_ENABLE);
/* ctx->Driver.Enable( ctx, GL_DEPTH_TEST, GL_FALSE )
*/
i915->meta.Ctx[I915_CTXREG_LIS6] &= ~(S6_DEPTH_TEST_ENABLE |
S6_DEPTH_WRITE_ENABLE);
/* ctx->Driver.StencilMask( ctx, s_mask )
*/
i915->meta.Ctx[I915_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_WRITE_MASK;
@ -504,8 +525,10 @@ void i915InitMetaFuncs( struct i915_context *i915 )
{
i915->intel.vtbl.install_meta_state = install_meta_state;
i915->intel.vtbl.leave_meta_state = leave_meta_state;
i915->intel.vtbl.meta_no_depth_stencil_write = meta_no_depth_stencil_write;
i915->intel.vtbl.meta_no_depth_write = meta_no_depth_write;
i915->intel.vtbl.meta_no_stencil_write = meta_no_stencil_write;
i915->intel.vtbl.meta_stencil_replace = meta_stencil_replace;
i915->intel.vtbl.meta_depth_replace = meta_depth_replace;
i915->intel.vtbl.meta_color_mask = meta_color_mask;
i915->intel.vtbl.meta_no_texture = meta_no_texture;
i915->intel.vtbl.meta_texture_blend_replace = meta_texture_blend_replace;

2
src/mesa/drivers/dri/i915/intel_blit.c
View file

@ -266,6 +266,8 @@ void intelClearWithBlit(GLcontext *ctx, GLbitfield flags, GLboolean all,
GLuint BR13, CMD, D_CMD;
BATCH_LOCALS;
if (INTEL_DEBUG & DEBUG_DRI)
_mesa_printf("%s %x\n", __FUNCTION__, flags);
clear_color = intel->ClearColor;
clear_depth = 0;

65
src/mesa/drivers/dri/i915/intel_buffers.c
View file

@ -213,19 +213,6 @@ void intelWindowMoved( struct intel_context *intel )
}
}
static void emit_clip_rect_quads(struct intel_context *intel,
const drm_clip_rect_t *clear)
{
/* XXX: Using INTEL_BATCH_NO_CLIPRECTS here is dangerous as the
* drawing origin may not be correctly emitted.
*/
intel_meta_draw_quad(intel,
clear->x1, clear->x2,
clear->y1, clear->y2,
0,
intel->ClearColor,
0, 0, 0, 0);
}
/* A true meta version of this would be very simple and additionally
@ -240,6 +227,9 @@ static void intelClearWithTris(struct intel_context *intel,
__DRIdrawablePrivate *dPriv = intel->driDrawable;
drm_clip_rect_t clear;
if (INTEL_DEBUG & DEBUG_DRI)
_mesa_printf("%s %x\n", __FUNCTION__, mask);
LOCK_HARDWARE(intel);
if (intel->driDrawable->numClipRects) {
@ -261,7 +251,7 @@ static void intelClearWithTris(struct intel_context *intel,
/* Back and stencil cliprects are the same. Try and do both
* buffers at once:
*/
if (mask & (BUFFER_BIT_BACK_LEFT|BUFFER_BIT_STENCIL)) {
if (mask & (BUFFER_BIT_BACK_LEFT|BUFFER_BIT_STENCIL|BUFFER_BIT_DEPTH)) {
intel->vtbl.meta_draw_region(intel,
intel->back_region,
intel->depth_region );
@ -276,23 +266,43 @@ static void intelClearWithTris(struct intel_context *intel,
intel->ctx.Stencil.WriteMask[0],
intel->ctx.Stencil.Clear);
else
intel->vtbl.meta_no_depth_stencil_write(intel);
intel->vtbl.meta_no_stencil_write(intel);
if (mask & BUFFER_BIT_DEPTH)
intel->vtbl.meta_depth_replace( intel );
else
intel->vtbl.meta_no_depth_write(intel);
/* Do cliprects explicitly:
/* XXX: Using INTEL_BATCH_NO_CLIPRECTS here is dangerous as the
* drawing origin may not be correctly emitted.
*/
emit_clip_rect_quads(intel, &clear);
intel_meta_draw_quad(intel,
clear.x1, clear.x2,
clear.y1, clear.y2,
intel->ctx.Depth.Clear,
intel->ClearColor,
0, 0, 0, 0);
}
/* Front may have different cliprects:
*/
if (mask & BUFFER_BIT_FRONT_LEFT) {
intel->vtbl.meta_no_depth_stencil_write(intel);
intel->vtbl.meta_no_depth_write(intel);
intel->vtbl.meta_no_stencil_write(intel);
intel->vtbl.meta_color_mask(intel, GL_TRUE );
intel->vtbl.meta_draw_region(intel,
intel->front_region,
intel->depth_region);
emit_clip_rect_quads(intel, &clear);
/* XXX: Using INTEL_BATCH_NO_CLIPRECTS here is dangerous as the
* drawing origin may not be correctly emitted.
*/
intel_meta_draw_quad(intel,
clear.x1, clear.x2,
clear.y1, clear.y2,
0,
intel->ClearColor,
0, 0, 0, 0);
}
intel->vtbl.leave_meta_state( intel );
@ -339,15 +349,12 @@ static void intelClear(GLcontext *ctx,
}
}
if (mask & BUFFER_BIT_DEPTH) {
blit_mask |= BUFFER_BIT_DEPTH;
}
if (mask & BUFFER_BIT_STENCIL) {
if (!intel->hw_stencil) {
swrast_mask |= BUFFER_BIT_STENCIL;
}
else if (ctx->Stencil.WriteMask[0] != 0xff) {
else if ((ctx->Stencil.WriteMask[0] & 0xff) != 0xff) {
tri_mask |= BUFFER_BIT_STENCIL;
}
else {
@ -355,11 +362,21 @@ static void intelClear(GLcontext *ctx,
}
}
/* Do depth with stencil if possible to avoid 2nd pass over the
* same buffer.
*/
if (mask & BUFFER_BIT_DEPTH) {
if (tri_mask & BUFFER_BIT_STENCIL)
tri_mask |= BUFFER_BIT_DEPTH;
else
blit_mask |= BUFFER_BIT_DEPTH;
}
swrast_mask |= (mask & BUFFER_BIT_ACCUM);
intelFlush( ctx );
if (blit_mask)
if (blit_mask)
intelClearWithBlit( ctx, blit_mask, all, cx, cy, cw, ch );
if (tri_mask)

5
src/mesa/drivers/dri/i915/intel_bufmgr.c
View file

@ -162,8 +162,11 @@ bmDeleteBuffers(struct bufmgr *bm, unsigned n, unsigned *buffers)
unsigned i;
for (i = 0; i < n; i++) {
drmMMBuf *buf = _mesa_HashLookup(bm->hash, buffers[i]);
if (buf) {
drmMMFreeBuffer(bm->driFd, buf);
drmMMFreeBuffer(bm->driFd, buf);
_mesa_HashRemove(bm->hash, buffers[i]);
}
}
}
UNLOCK(bm);

7
src/mesa/drivers/dri/i915/intel_context.h
View file

@ -144,11 +144,14 @@ struct intel_context
GLuint mask,
GLuint clear );
void (*meta_no_depth_stencil_write)( struct intel_context *intel );
void (*meta_depth_replace)( struct intel_context *intel );
void (*meta_no_texture)( struct intel_context *intel );
void (*meta_texture_blend_replace)( struct intel_context *intel );
void (*meta_no_stencil_write)( struct intel_context *intel );
void (*meta_no_depth_write)( struct intel_context *intel );
void (*meta_no_texture)( struct intel_context *intel );
void (*meta_import_pixel_state)( struct intel_context *intel );
GLboolean (*meta_tex_rect_source)( struct intel_context *intel,

3
src/mesa/drivers/dri/i915/intel_pixel_copy.c
View file

@ -126,7 +126,8 @@ static GLboolean do_texture_copypixels( GLcontext *ctx,
/* Is this true? Also will need to turn depth testing on according
* to state:
*/
intel->vtbl.meta_no_depth_stencil_write(intel);
intel->vtbl.meta_no_stencil_write(intel);
intel->vtbl.meta_no_depth_write(intel);
/* Set the 3d engine to draw into the destination region:
*/

3
src/mesa/drivers/dri/i915/intel_pixel_draw.c
View file

@ -105,7 +105,8 @@ static GLboolean do_texture_drawpixels( GLcontext *ctx,
/* Is this true? Also will need to turn depth testing on according
* to state:
*/
intel->vtbl.meta_no_depth_stencil_write(intel);
intel->vtbl.meta_no_stencil_write(intel);
intel->vtbl.meta_no_depth_write(intel);
/* Set the 3d engine to draw into the destination region:
*/

3
src/mesa/drivers/dri/i915/intel_pixel_read.c
View file

@ -113,7 +113,8 @@ do_texture_readpixels( GLcontext *ctx,
if (intel->driDrawable->numClipRects) {
intel->vtbl.install_meta_state(intel);
intel->vtbl.meta_no_depth_stencil_write(intel);
intel->vtbl.meta_no_depth_write(intel);
intel->vtbl.meta_no_stencil_write(intel);
if (!driClipRectToFramebuffer(ctx->ReadBuffer, &x, &y, &width, &height)) {
UNLOCK_HARDWARE( intel );

6
src/mesa/drivers/dri/i915/intel_tris.c
View file

@ -977,10 +977,10 @@ void intel_meta_draw_quad(struct intel_context *intel,
{
union fi *vb;
if (0)
fprintf(stderr, "%s: %f,%f-%f,%f 0x%x %f,%f-%f,%f\n",
if (INTEL_DEBUG & DEBUG_DRI)
fprintf(stderr, "%s: %f,%f-%f,%f 0x%x %f,%f-%f,%f depth: %f\n",
__FUNCTION__,
x0,y0,x1,y1,color,s0,t0,s1,t1);
x0,y0,x1,y1,color,s0,t0,s1,t1, z);
intel->vtbl.emit_state( intel );