diff --git a/src/intel/compiler/brw_analysis.h b/src/intel/compiler/brw_analysis.h
index 7e3fef77a81..7f9c6757c0b 100644
--- a/src/intel/compiler/brw_analysis.h
+++ b/src/intel/compiler/brw_analysis.h
@@ -237,6 +237,12 @@ struct brw_range {
    int start;
    int end;
 
+   /* If range not empty, this is the last value inside the range. */
+   inline int last() const
+   {
+      return end;
+   }
+
    inline bool is_empty() const
    {
       return end < start;
diff --git a/src/intel/compiler/brw_analysis_liveness.cpp b/src/intel/compiler/brw_analysis_liveness.cpp
index 47b1934adc3..3ed80953b21 100644
--- a/src/intel/compiler/brw_analysis_liveness.cpp
+++ b/src/intel/compiler/brw_analysis_liveness.cpp
@@ -234,7 +234,7 @@ brw_live_variables::compute_start_end()
          vars_range[i] = merge(vars_range[i], bd->ip_range.start);
 
       BITSET_FOREACH_SET(i, bd->liveout, (unsigned)num_vars)
-         vars_range[i] = merge(vars_range[i], bd->ip_range.end);
+         vars_range[i] = merge(vars_range[i], bd->ip_range.last());
    }
 }
 
diff --git a/src/intel/compiler/brw_lower_scoreboard.cpp b/src/intel/compiler/brw_lower_scoreboard.cpp
index f4594cc5bb7..80bb0f1c0ab 100644
--- a/src/intel/compiler/brw_lower_scoreboard.cpp
+++ b/src/intel/compiler/brw_lower_scoreboard.cpp
@@ -1143,7 +1143,7 @@ namespace {
 
                   for (unsigned p = 0; p < IDX(TGL_PIPE_ALL); p++)
                      delta[p] = jps[ips.range(child_link->block).start].jp[p]
-                        - jps[ips.range(block).end].jp[p]
+                        - jps[ips.range(block).last()].jp[p]
                         - ordered_unit(shader->devinfo,
                                        static_cast<const brw_inst *>(block->end()), p);
 
diff --git a/src/intel/compiler/brw_opt_register_coalesce.cpp b/src/intel/compiler/brw_opt_register_coalesce.cpp
index 7bfb8ee7fbc..1515d0b635d 100644
--- a/src/intel/compiler/brw_opt_register_coalesce.cpp
+++ b/src/intel/compiler/brw_opt_register_coalesce.cpp
@@ -120,7 +120,7 @@ can_coalesce_vars(const intel_device_info *devinfo,
    assert(!intersection.is_empty());
 
    foreach_block(scan_block, cfg) {
-      if (ips.range(scan_block).end < intersection.start)
+      if (ips.range(scan_block).last() < intersection.start)
          continue;
 
       int scan_ip = ips.range(scan_block).start - 1;
@@ -140,7 +140,7 @@ can_coalesce_vars(const intel_device_info *devinfo,
             continue;
          }
 
-         if (scan_ip > intersection.end)
+         if (scan_ip > intersection.last())
             return true; /* registers do not interfere */
 
          if (seen_src_write && !seen_copy) {
diff --git a/src/intel/compiler/brw_reg_allocate.cpp b/src/intel/compiler/brw_reg_allocate.cpp
index 5443d0fb0ef..034d054dd5c 100644
--- a/src/intel/compiler/brw_reg_allocate.cpp
+++ b/src/intel/compiler/brw_reg_allocate.cpp
@@ -132,7 +132,7 @@ static int
 count_to_loop_end(const bblock_t *block, const brw_ip_ranges &ips)
 {
    if (block->end()->opcode == BRW_OPCODE_WHILE)
-      return ips.range(block).end;
+      return ips.range(block).last();
 
    int depth = 1;
    /* Skip the first block, since we don't want to count the do the calling
@@ -146,7 +146,7 @@ count_to_loop_end(const bblock_t *block, const brw_ip_ranges &ips)
       if (block->end()->opcode == BRW_OPCODE_WHILE) {
          depth--;
          if (depth == 0)
-            return ips.range(block).end;
+            return ips.range(block).last();
       }
    }
    unreachable("not reached");
@@ -1043,7 +1043,7 @@ brw_reg_alloc::set_spill_costs()
       if (isinf(spill_costs[i]))
          continue;
 
-      int live_length = live.vgrf_range[i].end - live.vgrf_range[i].start;
+      int live_length = live.vgrf_range[i].last() - live.vgrf_range[i].start;
       if (live_length <= 0)
          continue;
 
diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp
index ff1731661d3..2e580fae713 100644
--- a/src/intel/compiler/brw_schedule_instructions.cpp
+++ b/src/intel/compiler/brw_schedule_instructions.cpp
@@ -856,7 +856,7 @@ brw_instruction_scheduler::setup_liveness(cfg_t *cfg)
     */
    for (int block = 0; block < cfg->num_blocks - 1; block++) {
       for (int i = 0; i < grf_count; i++) {
-         const int block_end = ips.range(cfg->blocks[block]).end;
+         const int block_end = ips.range(cfg->blocks[block]).last();
          const brw_range vgrf_range = live.vgrf_range[i];
 
          if (vgrf_range.contains(block_end) &&
@@ -884,7 +884,7 @@ brw_instruction_scheduler::setup_liveness(cfg_t *cfg)
          if (range.start <= payload_last_use_ip[i])
             reg_pressure_in[block]++;
 
-         if (range.end <= payload_last_use_ip[i])
+         if (range.last() <= payload_last_use_ip[i])
             BITSET_SET(hw_liveout[block], i);
       }
    }