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pan/bi: Check dependencies of both destinations of instructions

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TEXC can have two destinations; the value for neither of them can be
used in the same bundle, so extend the code to check for this to
iterate over both destinations.

Fixes artefacts in the game "LIMBO".

Fixes: a303076c1a ("pan/bi: Add bi_instr_schedulable predicate")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15250>
(cherry picked from commit cb8c47b15e)
This commit is contained in:
Icecream95 2022-02-14 16:26:59 +13:00 • committed by Eric Engestrom
parent c627a2d201
commit 65021851cb
2 changed files with 15 additions and 10 deletions
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2
.pick_status.json
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@ -1822,7 +1822,7 @@
"description": "pan/bi: Check dependencies of both destinations of instructions",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "a303076c1ab71f92907b1967c4b542af0c847198"
},

23
src/panfrost/bifrost/bi_schedule.c
View file

@ -999,16 +999,21 @@ bi_instr_schedulable(bi_instr *instr,
* same clause (most likely they will not), so if a later instruction
* in the clause accesses the destination, the message-passing
* instruction can't be scheduled */
if (bi_opcode_props[instr->op].sr_write && !bi_is_null(instr->dest[0])) {
unsigned nr = bi_count_write_registers(instr, 0);
assert(instr->dest[0].type == BI_INDEX_REGISTER);
unsigned reg = instr->dest[0].value;
if (bi_opcode_props[instr->op].sr_write) {
bi_foreach_dest(instr, d) {
if (bi_is_null(instr->dest[d]))
continue;
for (unsigned i = 0; i < clause->access_count; ++i) {
bi_index idx = clause->accesses[i];
for (unsigned d = 0; d < nr; ++d) {
if (bi_is_equiv(bi_register(reg + d), idx))
return false;
unsigned nr = bi_count_write_registers(instr, d);
assert(instr->dest[d].type == BI_INDEX_REGISTER);
unsigned reg = instr->dest[d].value;
for (unsigned i = 0; i < clause->access_count; ++i) {
bi_index idx = clause->accesses[i];
for (unsigned d = 0; d < nr; ++d) {
if (bi_is_equiv(bi_register(reg + d), idx))
return false;
}
}
}
}