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freedreno/a3xx/compiler: add LIT
Needed by glxgears and etuxracer ;-) Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark
parent
cb9e07aa84
commit
64c134cedb
1 changed files with 142 additions and 3 deletions
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@ -65,10 +65,11 @@ static unsigned regmask_idx(struct ir3_register *reg)
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static void regmask_set(regmask_t regmask, struct ir3_register *reg,
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unsigned wrmask)
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{
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unsigned ridx = regmask_idx(reg) & ~0x3;
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unsigned i;
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for (i = 0; i < 4; i++) {
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if (wrmask & (1 << i)) {
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unsigned idx = regmask_idx(reg) + i;
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unsigned idx = ridx + i;
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regmask[idx / 8] |= 1 << (idx % 8);
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}
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}
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@ -179,8 +180,7 @@ compile_init(struct fd3_compile_context *ctx, struct fd3_shader_stateobj *so,
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ctx->info.file_max[TGSI_FILE_OUTPUT] + 1;
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so->first_immediate = ctx->base_reg[TGSI_FILE_IMMEDIATE];
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ctx->immediate_idx = 4 * (ctx->info.file_max[TGSI_FILE_CONSTANT] + 1 +
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ctx->info.file_max[TGSI_FILE_IMMEDIATE] + 1);
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ctx->immediate_idx = 4 * (ctx->info.file_max[TGSI_FILE_IMMEDIATE] + 1);
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ret = tgsi_parse_init(&ctx->parser, tokens);
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if (ret != TGSI_PARSE_OK)
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@ -602,6 +602,144 @@ vectorize(struct fd3_compile_context *ctx, struct ir3_instruction *instr,
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* native instructions:
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*/
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/* LIT - Light Coefficients:
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* dst.x = 1.0
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* dst.y = max(src.x, 0.0)
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* dst.z = (src.x > 0.0) ? max(src.y, 0.0)^{clamp(src.w, -128.0, 128.0))} : 0.0
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* dst.w = 1.0
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*
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* max.f tmp.y, src.y, {0.0}
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* nop
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* max.f tmp.z, src.w, {-128.0}
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* cmps.f.ge tmp.w, (neg)src.x, {0.0}
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* max.f dst.y, src.x, {0.0}
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* nop
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* min.f tmp.x, tmp.z, {128.0}
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* add.s tmp.z, tmp.w, -1
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* log2 tmp.y, tmp.y
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* (rpt1)nop
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* (ss)mul.f tmp.x, tmp.x, tmp.y
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* mov.f16f16 dst.x, {1.0}
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* mov.f16f16 dst.w, {1.0}
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* (rpt3)nop
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* exp2 tmp.x, tmp.x
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* (ss)sel.f16 dst.z, {0.0}, tmp.z, tmp.x
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*/
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static void
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trans_lit(const struct instr_translater *t,
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struct fd3_compile_context *ctx,
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struct tgsi_full_instruction *inst)
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{
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struct ir3_instruction *instr;
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struct ir3_register *r;
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struct tgsi_dst_register tmp_dst;
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struct tgsi_src_register *tmp_src;
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struct tgsi_src_register constval0, constval1, constval128;
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struct tgsi_src_register *src = &inst->Src[0].Register;
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struct tgsi_dst_register *dst = get_dst(ctx, inst);
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tmp_src = get_internal_temp_repl(ctx, &tmp_dst);
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if (is_const(src))
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src = get_unconst(ctx, src);
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get_immediate(ctx, &constval0, fui(0.0));
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get_immediate(ctx, &constval1, fui(1.0));
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get_immediate(ctx, &constval128, fui(128.0));
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/* max.f tmp.y, src.y, {0.0} */
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instr = ir3_instr_create(ctx->ir, 2, OPC_MAX_F);
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add_dst_reg(ctx, instr, &tmp_dst, TGSI_SWIZZLE_Y);
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add_src_reg(ctx, instr, src, TGSI_SWIZZLE_Y);
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add_src_reg(ctx, instr, &constval0, constval0.SwizzleX);
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/* nop */
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ir3_instr_create(ctx->ir, 0, OPC_NOP);
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/* max.f tmp.z, src.w, {-128.0} */
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instr = ir3_instr_create(ctx->ir, 2, OPC_MAX_F);
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add_dst_reg(ctx, instr, &tmp_dst, TGSI_SWIZZLE_Z);
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add_src_reg(ctx, instr, src, TGSI_SWIZZLE_W);
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add_src_reg(ctx, instr, &constval128,
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constval128.SwizzleX)->flags |= IR3_REG_NEGATE;
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/* cmps.f.ge tmp.w, (neg)src.x, {0.0} */
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instr = ir3_instr_create(ctx->ir, 2, OPC_CMPS_F);
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add_dst_reg(ctx, instr, &tmp_dst, TGSI_SWIZZLE_W);
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add_src_reg(ctx, instr, src, TGSI_SWIZZLE_X)->flags |= IR3_REG_NEGATE;
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add_src_reg(ctx, instr, &constval0, constval0.SwizzleX);
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instr->cat2.condition = IR3_COND_GE;
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/* max.f dst.y, src.x, {0.0} */
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instr = ir3_instr_create(ctx->ir, 2, OPC_MAX_F);
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add_dst_reg(ctx, instr, dst, TGSI_SWIZZLE_Y);
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add_src_reg(ctx, instr, src, TGSI_SWIZZLE_X);
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add_src_reg(ctx, instr, &constval0, constval0.SwizzleX);
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/* nop */
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ir3_instr_create(ctx->ir, 0, OPC_NOP);
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/* min.f tmp.x, tmp.z, {128.0} */
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instr = ir3_instr_create(ctx->ir, 2, OPC_MIN_F);
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add_dst_reg(ctx, instr, &tmp_dst, TGSI_SWIZZLE_X);
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add_src_reg(ctx, instr, tmp_src, TGSI_SWIZZLE_Z);
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add_src_reg(ctx, instr, &constval128, constval128.SwizzleX);
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/* add.s tmp.z, tmp.w, -1 */
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instr = ir3_instr_create(ctx->ir, 2, OPC_ADD_S);
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add_dst_reg(ctx, instr, &tmp_dst, TGSI_SWIZZLE_Z);
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add_src_reg(ctx, instr, tmp_src, TGSI_SWIZZLE_W);
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ir3_reg_create(instr, 0, IR3_REG_IMMED)->iim_val = -1;
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/* log2 tmp.y, tmp.y */
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instr = ir3_instr_create(ctx->ir, 4, OPC_LOG2);
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r = add_dst_reg(ctx, instr, &tmp_dst, TGSI_SWIZZLE_Y);
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add_src_reg(ctx, instr, tmp_src, TGSI_SWIZZLE_Y);
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regmask_set(ctx->needs_ss, r, TGSI_WRITEMASK_Y);
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/* (rpt1)nop */
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ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 1;
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/* (ss)mul.f tmp.x, tmp.x, tmp.y */
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instr = ir3_instr_create(ctx->ir, 2, OPC_MUL_F);
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add_dst_reg(ctx, instr, &tmp_dst, TGSI_SWIZZLE_X);
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add_src_reg(ctx, instr, tmp_src, TGSI_SWIZZLE_X);
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add_src_reg(ctx, instr, tmp_src, TGSI_SWIZZLE_Y);
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/* mov.f16f16 dst.x, {1.0} */
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instr = ir3_instr_create(ctx->ir, 1, 0);
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instr->cat1.src_type = get_ftype(ctx);
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instr->cat1.dst_type = get_ftype(ctx);
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add_dst_reg(ctx, instr, dst, TGSI_SWIZZLE_X);
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add_src_reg(ctx, instr, &constval1, constval1.SwizzleX);
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/* mov.f16f16 dst.w, {1.0} */
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instr = ir3_instr_create(ctx->ir, 1, 0);
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instr->cat1.src_type = get_ftype(ctx);
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instr->cat1.dst_type = get_ftype(ctx);
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add_dst_reg(ctx, instr, dst, TGSI_SWIZZLE_W);
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add_src_reg(ctx, instr, &constval1, constval1.SwizzleX);
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/* (rpt3)nop */
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ir3_instr_create(ctx->ir, 0, OPC_NOP)->repeat = 3;
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/* exp2 tmp.x, tmp.x */
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instr = ir3_instr_create(ctx->ir, 4, OPC_EXP2);
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r = add_dst_reg(ctx, instr, &tmp_dst, TGSI_SWIZZLE_X);
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add_src_reg(ctx, instr, tmp_src, TGSI_SWIZZLE_X);
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regmask_set(ctx->needs_ss, r, TGSI_WRITEMASK_X);
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/* (ss)sel.f16 dst.z, {0.0}, tmp.z, tmp.x */
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instr = ir3_instr_create(ctx->ir, 3,
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ctx->so->half_precision ? OPC_SEL_F16 : OPC_SEL_F32);
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add_dst_reg(ctx, instr, dst, TGSI_SWIZZLE_Z);
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add_src_reg(ctx, instr, &constval0, constval0.SwizzleX);
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add_src_reg(ctx, instr, tmp_src, TGSI_SWIZZLE_Z);
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add_src_reg(ctx, instr, tmp_src, TGSI_SWIZZLE_X);
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put_dst(ctx, inst, dst);
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}
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static inline void
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get_swiz(unsigned *swiz, struct tgsi_src_register *src)
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{
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@ -1266,6 +1404,7 @@ static const struct instr_translater translaters[TGSI_OPCODE_LAST] = {
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[TGSI_OPCODE_ ## n] = { .fxn = (f), .tgsi_opc = TGSI_OPCODE_ ## n, ##__VA_ARGS__ }
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INSTR(MOV, instr_cat1),
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INSTR(LIT, trans_lit),
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INSTR(RCP, instr_cat4, .opc = OPC_RCP),
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INSTR(RSQ, instr_cat4, .opc = OPC_RSQ),
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INSTR(SQRT, instr_cat4, .opc = OPC_SQRT),
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