mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-07 02:48:06 +02:00
radv: use LATE_Z for depth/stencil attachments used in feedback loops
To make sure shader invocations read the correct values.
Fixes dEQP-VK.rasterization.rasterization_order_attachment_access.*.samples_*.multi_draw_barriers
Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19728>
(cherry picked from commit a42f8d49c3)
This commit is contained in:
Samuel Pitoiset
Eric Engestrom
parent
3ef6b27bde
commit
648081624d
16 changed files with 75 additions and 118 deletions
|
|
@ -3523,7 +3523,7 @@
|
|||
"description": "radv: use LATE_Z for depth/stencil attachments used in feedback loops",
|
||||
"nominated": true,
|
||||
"nomination_type": 0,
|
||||
"resolution": 0,
|
||||
"resolution": 1,
|
||||
"main_sha": null,
|
||||
"because_sha": null
|
||||
},
|
||||
|
|
|
|||
|
|
@ -1,10 +1,3 @@
|
|||
# The following are a guess, based on polaris10
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.depth.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_2.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_4.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_8.multi_draw_barriers,Fail
|
||||
|
||||
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_2.d32_sfloat_s8_uint.stencil_max,Fail
|
||||
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_2.d32_sfloat_s8_uint.stencil_min,Fail
|
||||
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_2.d32_sfloat_s8_uint.stencil_zero,Fail
|
||||
|
|
|
|||
|
|
@ -8,11 +8,6 @@ dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.layer_copy_before_r
|
|||
dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.layer_copy_before_resolving.4_bit,Fail
|
||||
dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.layer_copy_before_resolving.8_bit,Fail
|
||||
dEQP-VK.pipeline.monolithic.timestamp.calibrated.calibration_test,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.depth.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_2.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_4.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_8.multi_draw_barriers,Fail
|
||||
dEQP-VK.texture.mipmap.2d.image_view_min_lod.base_level.linear_linear,Fail
|
||||
dEQP-VK.texture.mipmap.2d.image_view_min_lod.base_level.linear_linear_integer_texel_coord,Fail
|
||||
dEQP-VK.texture.mipmap.2d.image_view_min_lod.base_level.linear_nearest,Fail
|
||||
|
|
|
|||
|
|
@ -1,5 +0,0 @@
|
|||
dEQP-VK.rasterization.rasterization_order_attachment_access.depth.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_2.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_4.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_8.multi_draw_barriers,Fail
|
||||
|
|
@ -1,6 +0,0 @@
|
|||
# The following are a guess, based on navi10
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.depth.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_2.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_4.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_8.multi_draw_barriers,Fail
|
||||
|
|
@ -1,9 +1,3 @@
|
|||
dEQP-VK.rasterization.rasterization_order_attachment_access.depth.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_2.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_4.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_8.multi_draw_barriers,Fail
|
||||
|
||||
# New fails in CTS 1.3.3.0
|
||||
dEQP-VK.ray_tracing_pipeline.acceleration_structures.copy_within_pipeline.gpu.access_sbt_read,Crash
|
||||
dEQP-VK.ray_tracing_pipeline.acceleration_structures.copy_within_pipeline.gpu.stage_all_transfer,Crash
|
||||
|
|
|
|||
|
|
@ -1,9 +1,3 @@
|
|||
dEQP-VK.rasterization.rasterization_order_attachment_access.depth.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_2.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_4.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_8.multi_draw_barriers,Fail
|
||||
|
||||
dEQP-VK.graphicsfuzz.cov-fold-shift-gte32,Fail
|
||||
dEQP-VK.graphicsfuzz.cov-tail-duplicator-for-for-for,Fail
|
||||
|
||||
|
|
|
|||
|
|
@ -1,10 +1,3 @@
|
|||
# The following are a guess, based on navi21
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.depth.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_2.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_4.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_8.multi_draw_barriers,Fail
|
||||
|
||||
# New fails in CTS 1.3.3.0
|
||||
dEQP-VK.ray_tracing_pipeline.acceleration_structures.copy_within_pipeline.gpu.access_sbt_read,Crash
|
||||
dEQP-VK.ray_tracing_pipeline.acceleration_structures.copy_within_pipeline.gpu.stage_all_transfer,Crash
|
||||
|
|
|
|||
|
|
@ -26,11 +26,6 @@ dEQP-VK.texture.mipmap.3d.image_view_min_lod.base_level.nearest_nearest_integer_
|
|||
dEQP-VK.texture.mipmap.cubemap.image_view_min_lod.base_level.linear_nearest,Fail
|
||||
dEQP-VK.texture.mipmap.cubemap.image_view_min_lod.base_level.nearest_linear,Fail
|
||||
dEQP-VK.texture.mipmap.cubemap.image_view_min_lod.base_level.nearest_nearest,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.depth.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_2.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_4.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_8.multi_draw_barriers,Fail
|
||||
dEQP-VK.api.copy_and_blit.copy_commands2.resolve_image.layer_copy_before_resolving.2_bit_bind_offset,Fail
|
||||
dEQP-VK.api.copy_and_blit.copy_commands2.resolve_image.layer_copy_before_resolving.4_bit_bind_offset,Fail
|
||||
dEQP-VK.api.copy_and_blit.copy_commands2.resolve_image.layer_copy_before_resolving.8_bit_bind_offset,Fail
|
||||
|
|
|
|||
|
|
@ -1,8 +1,3 @@
|
|||
dEQP-VK.rasterization.rasterization_order_attachment_access.depth.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_2.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_4.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_8.multi_draw_barriers,Fail
|
||||
dEQP-VK.texture.mipmap.2d.image_view_min_lod.base_level.linear_linear,Fail
|
||||
dEQP-VK.texture.mipmap.2d.image_view_min_lod.base_level.linear_linear_integer_texel_coord,Fail
|
||||
dEQP-VK.texture.mipmap.2d.image_view_min_lod.base_level.linear_nearest,Fail
|
||||
|
|
|
|||
|
|
@ -1,6 +0,0 @@
|
|||
# The following are a guess, based on Renoir
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.depth.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_2.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_4.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_8.multi_draw_barriers,Fail
|
||||
|
|
@ -16,11 +16,6 @@ dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.diff_layout_copy_be
|
|||
dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.diff_layout_copy_before_resolving.8_bit_transfer_src_optimal_general,Fail
|
||||
dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_copy_before_resolving_compute.4_bit,Fail
|
||||
dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_copy_before_resolving_compute.8_bit,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.depth.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_2.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_4.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_8.multi_draw_barriers,Fail
|
||||
|
||||
# New fails in CTS 1.3.3.0
|
||||
dEQP-VK.api.copy_and_blit.copy_commands2.resolve_image.diff_layout_copy_before_resolving.4_bit_general_general_bind_offset,Fail
|
||||
|
|
|
|||
|
|
@ -394,7 +394,6 @@ dEQP-VK.dynamic_rendering.suballocation.unused_clear_attachments.colorunused_col
|
|||
dEQP-VK.dynamic_rendering.suballocation.unused_clear_attachments.colorused_colorused_colorused_colorused_stencilonly_d32s8_used,Fail
|
||||
dEQP-VK.dynamic_rendering.suballocation.unused_clear_attachments.colorused_stencilonly_d32s8_used,Fail
|
||||
dEQP-VK.pipeline.monolithic.timestamp.calibrated.calibration_test,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_4.multi_draw_barriers,Fail
|
||||
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_2.d16_unorm.depth_min,Fail
|
||||
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_2.d16_unorm.depth_zero,Fail
|
||||
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.samples_2.d32_sfloat.depth_min,Fail
|
||||
|
|
|
|||
|
|
@ -1,9 +1,3 @@
|
|||
dEQP-VK.rasterization.rasterization_order_attachment_access.depth.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_2.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_4.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_8.multi_draw_barriers,Fail
|
||||
|
||||
# New fails in CTS 1.3.3.0
|
||||
dEQP-VK.ray_tracing_pipeline.acceleration_structures.copy_within_pipeline.gpu.access_sbt_read,Crash
|
||||
dEQP-VK.ray_tracing_pipeline.acceleration_structures.copy_within_pipeline.gpu.stage_all_transfer,Crash
|
||||
|
|
|
|||
|
|
@ -16,11 +16,6 @@ dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.diff_layout_copy_be
|
|||
dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.diff_layout_copy_before_resolving.8_bit_transfer_src_optimal_general,Fail
|
||||
dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_copy_before_resolving_compute.4_bit,Fail
|
||||
dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_copy_before_resolving_compute.8_bit,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.depth.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_1.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_2.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_4.multi_draw_barriers,Fail
|
||||
dEQP-VK.rasterization.rasterization_order_attachment_access.stencil.samples_8.multi_draw_barriers,Fail
|
||||
|
||||
# New fails in CTS 1.3.3.0
|
||||
dEQP-VK.api.copy_and_blit.copy_commands2.resolve_image.diff_layout_copy_before_resolving.4_bit_general_general_bind_offset,Fail
|
||||
|
|
|
|||
|
|
@ -39,6 +39,7 @@
|
|||
#include "radv_shader.h"
|
||||
#include "radv_shader_args.h"
|
||||
#include "vk_pipeline.h"
|
||||
#include "vk_render_pass.h"
|
||||
#include "vk_util.h"
|
||||
|
||||
#include "util/u_debug.h"
|
||||
|
|
@ -72,6 +73,7 @@ struct radv_blend_state {
|
|||
struct radv_depth_stencil_state {
|
||||
uint32_t db_render_control;
|
||||
uint32_t db_render_override2;
|
||||
uint32_t db_shader_control;
|
||||
};
|
||||
|
||||
struct radv_dsa_order_invariance {
|
||||
|
|
@ -1931,9 +1933,75 @@ radv_pipeline_init_dynamic_state(struct radv_graphics_pipeline *pipeline,
|
|||
pipeline->dynamic_state.mask = states;
|
||||
}
|
||||
|
||||
static bool
|
||||
radv_pipeline_uses_ds_feedback_loop(const VkGraphicsPipelineCreateInfo *pCreateInfo,
|
||||
const struct vk_graphics_pipeline_state *state)
|
||||
{
|
||||
VK_FROM_HANDLE(vk_render_pass, render_pass, state->rp->render_pass);
|
||||
|
||||
if (render_pass) {
|
||||
uint32_t subpass_idx = state->rp->subpass;
|
||||
struct vk_subpass *subpass = &render_pass->subpasses[subpass_idx];
|
||||
struct vk_subpass_attachment *ds_att = subpass->depth_stencil_attachment;
|
||||
|
||||
for (uint32_t i = 0; i < subpass->input_count; i++) {
|
||||
if (ds_att && ds_att->attachment == subpass->input_attachments[i].attachment) {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return (pCreateInfo->flags & VK_PIPELINE_CREATE_DEPTH_STENCIL_ATTACHMENT_FEEDBACK_LOOP_BIT_EXT) != 0;
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
radv_compute_db_shader_control(const struct radv_graphics_pipeline *pipeline,
|
||||
const struct vk_graphics_pipeline_state *state,
|
||||
const VkGraphicsPipelineCreateInfo *pCreateInfo)
|
||||
{
|
||||
const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
|
||||
bool uses_ds_feedback_loop = radv_pipeline_uses_ds_feedback_loop(pCreateInfo, state);
|
||||
struct radv_shader *ps = pipeline->base.shaders[MESA_SHADER_FRAGMENT];
|
||||
unsigned conservative_z_export = V_02880C_EXPORT_ANY_Z;
|
||||
unsigned z_order;
|
||||
|
||||
/* When a depth/stencil attachment is used inside feedback loops, use LATE_Z to make sure shader
|
||||
* invocations read the correct value.
|
||||
*/
|
||||
if (!uses_ds_feedback_loop && (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory))
|
||||
z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
|
||||
else
|
||||
z_order = V_02880C_LATE_Z;
|
||||
|
||||
if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_GREATER)
|
||||
conservative_z_export = V_02880C_EXPORT_GREATER_THAN_Z;
|
||||
else if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_LESS)
|
||||
conservative_z_export = V_02880C_EXPORT_LESS_THAN_Z;
|
||||
|
||||
bool disable_rbplus = pdevice->rad_info.has_rbplus && !pdevice->rad_info.rbplus_allowed;
|
||||
|
||||
/* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
|
||||
* but this appears to break Project Cars (DXVK). See
|
||||
* https://bugs.freedesktop.org/show_bug.cgi?id=109401
|
||||
*/
|
||||
bool mask_export_enable = ps->info.ps.writes_sample_mask;
|
||||
|
||||
return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
|
||||
S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
|
||||
S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
|
||||
S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
|
||||
S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export) | S_02880C_Z_ORDER(z_order) |
|
||||
S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
|
||||
S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
|
||||
S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
|
||||
S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
|
||||
S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
|
||||
}
|
||||
|
||||
static struct radv_depth_stencil_state
|
||||
radv_pipeline_init_depth_stencil_state(struct radv_graphics_pipeline *pipeline,
|
||||
const struct vk_graphics_pipeline_state *state)
|
||||
const struct vk_graphics_pipeline_state *state,
|
||||
const VkGraphicsPipelineCreateInfo *pCreateInfo)
|
||||
{
|
||||
const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
|
||||
struct radv_depth_stencil_state ds_state = {0};
|
||||
|
|
@ -1949,6 +2017,8 @@ radv_pipeline_init_depth_stencil_state(struct radv_graphics_pipeline *pipeline,
|
|||
ds_state.db_render_override2 |= S_028010_CENTROID_COMPUTATION_MODE(1);
|
||||
}
|
||||
|
||||
ds_state.db_shader_control = radv_compute_db_shader_control(pipeline, state, pCreateInfo);
|
||||
|
||||
if (pdevice->rad_info.gfx_level >= GFX11) {
|
||||
unsigned max_allowed_tiles_in_wave = 0;
|
||||
unsigned num_samples = MAX2(radv_pipeline_color_samples(state),
|
||||
|
|
@ -4765,6 +4835,8 @@ radv_pipeline_emit_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
|
|||
radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, ds_state->db_render_control);
|
||||
|
||||
radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, ds_state->db_render_override2);
|
||||
|
||||
radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL, ds_state->db_shader_control);
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -5442,43 +5514,6 @@ radv_pipeline_emit_ps_inputs(struct radeon_cmdbuf *ctx_cs,
|
|||
}
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
radv_compute_db_shader_control(const struct radv_physical_device *pdevice,
|
||||
const struct radv_graphics_pipeline *pipeline,
|
||||
const struct radv_shader *ps)
|
||||
{
|
||||
unsigned conservative_z_export = V_02880C_EXPORT_ANY_Z;
|
||||
unsigned z_order;
|
||||
if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
|
||||
z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
|
||||
else
|
||||
z_order = V_02880C_LATE_Z;
|
||||
|
||||
if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_GREATER)
|
||||
conservative_z_export = V_02880C_EXPORT_GREATER_THAN_Z;
|
||||
else if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_LESS)
|
||||
conservative_z_export = V_02880C_EXPORT_LESS_THAN_Z;
|
||||
|
||||
bool disable_rbplus = pdevice->rad_info.has_rbplus && !pdevice->rad_info.rbplus_allowed;
|
||||
|
||||
/* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
|
||||
* but this appears to break Project Cars (DXVK). See
|
||||
* https://bugs.freedesktop.org/show_bug.cgi?id=109401
|
||||
*/
|
||||
bool mask_export_enable = ps->info.ps.writes_sample_mask;
|
||||
|
||||
return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
|
||||
S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
|
||||
S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
|
||||
S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
|
||||
S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export) | S_02880C_Z_ORDER(z_order) |
|
||||
S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
|
||||
S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
|
||||
S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
|
||||
S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
|
||||
S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
|
||||
}
|
||||
|
||||
static void
|
||||
radv_pipeline_emit_fragment_shader(struct radeon_cmdbuf *ctx_cs, struct radeon_cmdbuf *cs,
|
||||
const struct radv_graphics_pipeline *pipeline)
|
||||
|
|
@ -5498,9 +5533,6 @@ radv_pipeline_emit_fragment_shader(struct radeon_cmdbuf *ctx_cs, struct radeon_c
|
|||
radeon_emit(cs, ps->config.rsrc1);
|
||||
radeon_emit(cs, ps->config.rsrc2);
|
||||
|
||||
radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
|
||||
radv_compute_db_shader_control(pdevice, pipeline, ps));
|
||||
|
||||
radeon_set_context_reg_seq(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA, 2);
|
||||
radeon_emit(ctx_cs, ps->config.spi_ps_input_ena);
|
||||
radeon_emit(ctx_cs, ps->config.spi_ps_input_addr);
|
||||
|
|
@ -6165,7 +6197,7 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv
|
|||
radv_pipeline_init_dynamic_state(pipeline, &state);
|
||||
|
||||
struct radv_depth_stencil_state ds_state =
|
||||
radv_pipeline_init_depth_stencil_state(pipeline, &state);
|
||||
radv_pipeline_init_depth_stencil_state(pipeline, &state, pCreateInfo);
|
||||
|
||||
if (device->physical_device->rad_info.gfx_level >= GFX10_3)
|
||||
gfx103_pipeline_init_vrs_state(pipeline, &state);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue