From 645fff5daed8121ffe54741020f402fe6cfa8818 Mon Sep 17 00:00:00 2001 From: Pierre-Eric Pelloux-Prayer Date: Mon, 15 Dec 2025 16:02:00 +0100 Subject: [PATCH] ac/descriptors: account for num_storage_samples for gfx10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes a page fault when nr_samples=4 but nr_storage_samples=2. Based on si_is_format_supported this is only supported for color formats and when has_eqaa_surface_allocator is true (< GFX11). The referenced commit below didn't introduce the issue but it exposed it by forcing the gfx blit path to be used. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13255 Fixes: 3424e16eced ("radeonsi: add decision code to select when to use CB_RESOLVE for performance") Reviewed-by: Marek Olšák Part-of: --- src/amd/common/ac_descriptors.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/amd/common/ac_descriptors.c b/src/amd/common/ac_descriptors.c index ebf4a7ef847..78e631d74ab 100644 --- a/src/amd/common/ac_descriptors.c +++ b/src/amd/common/ac_descriptors.c @@ -438,7 +438,11 @@ ac_build_gfx10_texture_descriptor(const struct radeon_info *info, const struct a const struct util_format_description *fmt_desc = util_format_description(state->format); const uint32_t img_format = ac_get_gfx10_img_format(info->gfx_level, state); const struct ac_surf_nbc_view *nbc_view = state->gfx10.nbc_view; - const uint32_t field_last_level = state->num_samples > 1 ? util_logbase2(state->num_samples) : state->last_level; + uint32_t num_samples; + + num_samples = fmt_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ? MAX2(1, state->num_samples) : + MAX2(1, state->num_storage_samples); + const uint32_t field_last_level = num_samples > 1 ? util_logbase2(num_samples) : state->last_level; desc[0] = 0; desc[1] = S_00A004_FORMAT_GFX10(img_format) | @@ -450,7 +454,7 @@ ac_build_gfx10_texture_descriptor(const struct radeon_info *info, const struct a S_00A00C_DST_SEL_Y(ac_map_swizzle(state->swizzle[1])) | S_00A00C_DST_SEL_Z(ac_map_swizzle(state->swizzle[2])) | S_00A00C_DST_SEL_W(ac_map_swizzle(state->swizzle[3])) | - S_00A00C_BASE_LEVEL(state->num_samples > 1 ? 0 : state->first_level) | + S_00A00C_BASE_LEVEL(num_samples > 1 ? 0 : state->first_level) | S_00A00C_LAST_LEVEL_GFX10(field_last_level) | S_00A00C_BC_SWIZZLE(ac_border_color_swizzle(fmt_desc)) | S_00A00C_TYPE(state->type); @@ -469,7 +473,7 @@ ac_build_gfx10_texture_descriptor(const struct radeon_info *info, const struct a desc[6] = 0; desc[7] = 0; - uint32_t max_mip = state->num_samples > 1 ? util_logbase2(state->num_samples) : state->num_levels - 1; + uint32_t max_mip = num_samples > 1 ? util_logbase2(num_samples) : state->num_levels - 1; if (nbc_view && nbc_view->valid) max_mip = nbc_view->num_levels - 1;