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iris: Use staging blits for reads from uncached buffers.

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If we're doing CPU reads of a resource that doesn't have CPU caches
enabled for the mapping (say, in device local memory, or WC mapped),
then blit it to a temporary that does have those caches enabled.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10941>
This commit is contained in:
Kenneth Graunke 2021-05-20 00:14:53 -07:00 • committed by Marge Bot
parent 49070038f4
commit 643c4ade4c
1 changed files with 5 additions and 1 deletions
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6
src/gallium/drivers/iris/iris_resource.c
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@ -2069,8 +2069,12 @@ iris_transfer_map(struct pipe_context *ctx,
if (fmtl->txc == ISL_TXC_ASTC)
usage |= PIPE_MAP_DIRECTLY;
/* We can map directly if it wouldn't stall, there's no compression,
* and we aren't doing an uncached read.
*/
if (!map_would_stall &&
!isl_aux_usage_has_compression(res->aux.usage)) {
!isl_aux_usage_has_compression(res->aux.usage) &&
!((usage & PIPE_MAP_READ) && !res->bo->cache_coherent)) {
usage |= PIPE_MAP_DIRECTLY;
}