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nvc0: backport fp helper invocation fix to 2nd gen Maxwell+

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Ben prefers that we use the firmware method where possible.

Cc: mesa-stable
Signed-off-by: Karol Herbst <git@karolherbst.de>
Acked-by: Dave Airlie <airlied@redhat.com>
Acked-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23802>
(cherry picked from commit 2c3b624300)
This commit is contained in:
Karol Herbst 2023-06-22 16:43:40 +02:00 • committed by Eric Engestrom
parent 59a2836117
commit 642308dc18
4 changed files with 80 additions and 3 deletions
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2
.pick_status.json
View file

@ -1345,7 +1345,7 @@
"description": "nvc0: backport fp helper invocation fix to 2nd gen Maxwell+",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null
},

41
src/gallium/drivers/nouveau/nvc0/mme/com9097.mme
View file

@ -581,6 +581,47 @@ crs_loop:
exit maddr 0x1452 /* CONSERVATIVE_RASTER */
send 0x1
/* NVC0_3D_MACRO_SET_PRIV_REG
*
* Requests the GR Falcon to set a MMIO register.
*
* arg = register
* param[0] = value
* param[1] = mask
*/
.section #mme9097_set_priv_reg
maddr 0x1044 /* WAIT_FOR_IDLE */
send 0x0
parm $r2 /* value */
parm $r3 /* mask */
maddr 0x1d00 /* SCRATCH[0] */
send 0x0
send $r2
send $r3
read $r2 0xd1a /* SCRATCH[26] */
maddr 0x18c4 /* FIRMWARE[4] */
send $r1
mov $r1 (extrinsrt 0x0 $r2 0 8 0)
mov $r1 (add $r1 -2)
/* Set it to 0 increment for later sends */
maddr 0x0040 /* NO_OPERATION */
branz annul $r1 #spr_unk_else
spr_wait_loop:
read $r1 0xd00 /* SCRATCH(0) */
send 0x0
mov $r1 (add $r1 -1)
branz annul $r1 #spr_wait_loop
bra annul #spr_exit
spr_unk_else:
mov $r1 10
spr_unk_else_loop:
send 0x0
mov $r1 (add $r1 -1)
branz annul $r1 #spr_unk_else_loop
spr_exit:
exit mov $r1 $r1
mov $r1 $r1
/* NVC0_3D_MACRO_COMPUTE_COUNTER
*
* This macro takes 6 values, num_groups_* and group_size_*, and adds their

33
src/gallium/drivers/nouveau/nvc0/mme/com9097.mme.h
View file

@ -395,6 +395,39 @@ const uint32_t mme9097_conservative_raster_state[] = {
0x00004041,
};
const uint32_t mme9097_set_priv_reg[] = {
0x04110021,
0x00000041,
0x00000201,
/* 0x000f: spr_wait_loop */
0x00000301,
0x07400021,
/* 0x0014: spr_unk_else */
/* 0x0015: spr_unk_else_loop */
0x00000041,
/* 0x0018: spr_exit */
0x00001041,
0x00001841,
0x03468215,
0x06310021,
0x00000841,
0x02008112,
0xffff8911,
0x00100021,
0x00018837,
0x03400115,
0x00000041,
0xffffc911,
0xffff4837,
0x00014027,
0x00028111,
0x00000041,
0xffffc911,
0xffff88b7,
0x00000991,
0x00000911,
};
const uint32_t mme9097_compute_counter[] = {
/* 0x0003: iic_loop_start */
0x00000f11,

7
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
View file

@ -1364,6 +1364,7 @@ nvc0_screen_create(struct nouveau_device *dev)
MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
MK_MACRO(NVC0_3D_MACRO_SET_PRIV_REG, mme9097_set_priv_reg);
MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER, mme9097_compute_counter);
MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER_TO_QUERY, mme9097_compute_counter_to_query);
MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
@ -1462,9 +1463,11 @@ nvc0_screen_create(struct nouveau_device *dev)
BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
PUSH_DATA (push, 0);
if (screen->eng3d->oclass >= TU102_3D_CLASS) {
/* requires Nvidia provided firmware */
if (screen->eng3d->oclass >= GM200_3D_CLASS) {
unsigned reg = screen->eng3d->oclass >= GV100_3D_CLASS ? 0x419ba4 : 0x419f78;
BEGIN_1IC0(push, NVC0_3D(MACRO_SET_PRIV_REG), 3);
PUSH_DATA (push, 0x419ba4);
PUSH_DATA (push, reg);
PUSH_DATA (push, 0x00000000);
PUSH_DATA (push, 0x00000008);
}