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radv/video: Support encoding multiple slices
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12285 Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35070>
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2 changed files with 9 additions and 4 deletions
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@ -750,7 +750,7 @@ radv_GetPhysicalDeviceVideoCapabilitiesKHR(VkPhysicalDevice physicalDevice, cons
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ext->flags = VK_VIDEO_ENCODE_H264_CAPABILITY_HRD_COMPLIANCE_BIT_KHR |
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ext->flags = VK_VIDEO_ENCODE_H264_CAPABILITY_HRD_COMPLIANCE_BIT_KHR |
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VK_VIDEO_ENCODE_H264_CAPABILITY_PER_PICTURE_TYPE_MIN_MAX_QP_BIT_KHR;
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VK_VIDEO_ENCODE_H264_CAPABILITY_PER_PICTURE_TYPE_MIN_MAX_QP_BIT_KHR;
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ext->maxLevelIdc = cap ? cap->max_level : 0;
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ext->maxLevelIdc = cap ? cap->max_level : 0;
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ext->maxSliceCount = 1;
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ext->maxSliceCount = 128;
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ext->maxPPictureL0ReferenceCount = 1;
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ext->maxPPictureL0ReferenceCount = 1;
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ext->maxBPictureL0ReferenceCount = pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_3 ? 1 : 0;
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ext->maxBPictureL0ReferenceCount = pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_3 ? 1 : 0;
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ext->maxL1ReferenceCount = pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_3 ? 1 : 0;
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ext->maxL1ReferenceCount = pdev->enc_hw_ver >= RADV_VIDEO_ENC_HW_3 ? 1 : 0;
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@ -795,7 +795,7 @@ radv_GetPhysicalDeviceVideoCapabilitiesKHR(VkPhysicalDevice physicalDevice, cons
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ext->flags = VK_VIDEO_ENCODE_H265_CAPABILITY_PER_PICTURE_TYPE_MIN_MAX_QP_BIT_KHR;
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ext->flags = VK_VIDEO_ENCODE_H265_CAPABILITY_PER_PICTURE_TYPE_MIN_MAX_QP_BIT_KHR;
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ext->maxLevelIdc = cap ? cap->max_level : 0;
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ext->maxLevelIdc = cap ? cap->max_level : 0;
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ext->maxSliceSegmentCount = 1;
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ext->maxSliceSegmentCount = 128;
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ext->maxTiles.width = 1;
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ext->maxTiles.width = 1;
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ext->maxTiles.height = 1;
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ext->maxTiles.height = 1;
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ext->ctbSizes = VK_VIDEO_ENCODE_H265_CTB_SIZE_64_BIT_KHR;
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ext->ctbSizes = VK_VIDEO_ENCODE_H265_CTB_SIZE_64_BIT_KHR;
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@ -426,11 +426,13 @@ radv_enc_slice_control(struct radv_cmd_buffer *cmd_buffer, const struct VkVideoE
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{
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{
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struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
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struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
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const struct radv_physical_device *pdev = radv_device_physical(device);
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const struct radv_physical_device *pdev = radv_device_physical(device);
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const struct VkVideoEncodeH264PictureInfoKHR *h264_picture_info =
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vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H264_PICTURE_INFO_KHR);
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uint32_t num_mbs_in_slice;
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uint32_t num_mbs_in_slice;
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uint32_t width_in_mbs = DIV_ROUND_UP(enc_info->srcPictureResource.codedExtent.width, 16);
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uint32_t width_in_mbs = DIV_ROUND_UP(enc_info->srcPictureResource.codedExtent.width, 16);
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uint32_t height_in_mbs = DIV_ROUND_UP(enc_info->srcPictureResource.codedExtent.height, 16);
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uint32_t height_in_mbs = DIV_ROUND_UP(enc_info->srcPictureResource.codedExtent.height, 16);
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num_mbs_in_slice = width_in_mbs * height_in_mbs;
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num_mbs_in_slice = DIV_ROUND_UP(width_in_mbs * height_in_mbs, h264_picture_info->naluSliceEntryCount);
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RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.slice_control_h264);
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RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.slice_control_h264);
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RADEON_ENC_CS(RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS); // slice control mode
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RADEON_ENC_CS(RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS); // slice control mode
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@ -503,12 +505,14 @@ radv_enc_slice_control_hevc(struct radv_cmd_buffer *cmd_buffer, const struct VkV
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{
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{
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struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
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struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
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const struct radv_physical_device *pdev = radv_device_physical(device);
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const struct radv_physical_device *pdev = radv_device_physical(device);
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const struct VkVideoEncodeH265PictureInfoKHR *h265_picture_info =
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vk_find_struct_const(enc_info->pNext, VIDEO_ENCODE_H265_PICTURE_INFO_KHR);
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uint32_t width_in_ctb, height_in_ctb, num_ctbs_in_slice;
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uint32_t width_in_ctb, height_in_ctb, num_ctbs_in_slice;
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width_in_ctb = DIV_ROUND_UP(enc_info->srcPictureResource.codedExtent.width, 64);
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width_in_ctb = DIV_ROUND_UP(enc_info->srcPictureResource.codedExtent.width, 64);
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height_in_ctb = DIV_ROUND_UP(enc_info->srcPictureResource.codedExtent.height, 64);
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height_in_ctb = DIV_ROUND_UP(enc_info->srcPictureResource.codedExtent.height, 64);
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num_ctbs_in_slice = width_in_ctb * height_in_ctb;
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num_ctbs_in_slice = DIV_ROUND_UP(width_in_ctb * height_in_ctb, h265_picture_info->naluSliceSegmentEntryCount);
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RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.slice_control_hevc);
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RADEON_ENC_BEGIN(pdev->vcn_enc_cmds.slice_control_hevc);
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RADEON_ENC_CS(RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS);
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RADEON_ENC_CS(RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS);
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@ -1881,6 +1885,7 @@ radv_video_patch_encode_session_parameters(struct vk_video_session_parameters *p
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params->h265_enc.h265_pps[i].base.flags.cu_qp_delta_enabled_flag = 1;
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params->h265_enc.h265_pps[i].base.flags.cu_qp_delta_enabled_flag = 1;
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params->h265_enc.h265_pps[i].base.diff_cu_qp_delta_depth = 0;
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params->h265_enc.h265_pps[i].base.diff_cu_qp_delta_depth = 0;
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params->h265_enc.h265_pps[i].base.init_qp_minus26 = 0;
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params->h265_enc.h265_pps[i].base.init_qp_minus26 = 0;
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params->h265_enc.h265_pps[i].base.flags.dependent_slice_segments_enabled_flag = 1;
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}
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}
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break;
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break;
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}
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}
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