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radeonsi: move DB_RENDER_CONTROL into draw_vbo

Browse source 
So that I can add fast depth clear.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Marek Olšák 2014-08-23 03:25:29 +02:00
parent 78aa717601
commit 63cb4077e6
5 changed files with 46 additions and 58 deletions
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35
src/gallium/drivers/radeonsi/si_blit.c
View file

@ -114,7 +114,6 @@ static void si_blit_decompress_depth(struct pipe_context *ctx,
unsigned layer, level, sample, checked_last_layer, max_layer, max_sample;
float depth = 1.0f;
const struct util_format_description *desc;
void **custom_dsa;
struct r600_texture *flushed_depth_texture = staging ?
staging : texture->flushed_depth_texture;
@ -124,20 +123,13 @@ static void si_blit_decompress_depth(struct pipe_context *ctx,
max_sample = u_max_sample(&texture->resource.b.b);
desc = util_format_description(flushed_depth_texture->resource.b.b.format);
switch (util_format_has_depth(desc) | util_format_has_stencil(desc) << 1) {
default:
assert(!"No depth or stencil to uncompress");
return;
case 3:
custom_dsa = sctx->custom_dsa_flush_depth_stencil;
break;
case 2:
custom_dsa = sctx->custom_dsa_flush_stencil;
break;
case 1:
custom_dsa = sctx->custom_dsa_flush_depth;
break;
}
if (util_format_has_depth(desc))
sctx->dbcb_depth_copy_enabled = true;
if (util_format_has_stencil(desc))
sctx->dbcb_stencil_copy_enabled = true;
assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
for (level = first_level; level <= last_level; level++) {
if (!staging && !(texture->dirty_level_mask & (1 << level)))
@ -152,6 +144,8 @@ static void si_blit_decompress_depth(struct pipe_context *ctx,
for (sample = first_sample; sample <= last_sample; sample++) {
struct pipe_surface *zsurf, *cbsurf, surf_tmpl;
sctx->dbcb_copy_sample = sample;
surf_tmpl.format = texture->resource.b.b.format;
surf_tmpl.u.tex.level = level;
surf_tmpl.u.tex.first_layer = layer;
@ -165,7 +159,7 @@ static void si_blit_decompress_depth(struct pipe_context *ctx,
si_blitter_begin(ctx, SI_DECOMPRESS);
util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
custom_dsa[sample], depth);
sctx->custom_dsa_flush, depth);
si_blitter_end(ctx);
pipe_surface_reference(&zsurf, NULL);
@ -181,6 +175,9 @@ static void si_blit_decompress_depth(struct pipe_context *ctx,
texture->dirty_level_mask &= ~(1 << level);
}
}
sctx->dbcb_depth_copy_enabled = false;
sctx->dbcb_stencil_copy_enabled = false;
}
static void si_blit_decompress_depth_in_place(struct si_context *sctx,
@ -191,6 +188,8 @@ static void si_blit_decompress_depth_in_place(struct si_context *sctx,
struct pipe_surface *zsurf, surf_tmpl = {{0}};
unsigned layer, max_layer, checked_last_layer, level;
sctx->db_inplace_flush_enabled = true;
surf_tmpl.format = texture->resource.b.b.format;
for (level = first_level; level <= last_level; level++) {
@ -212,7 +211,7 @@ static void si_blit_decompress_depth_in_place(struct si_context *sctx,
si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
sctx->custom_dsa_flush_inplace,
sctx->custom_dsa_flush,
1.0f);
si_blitter_end(&sctx->b.b);
@ -225,6 +224,8 @@ static void si_blit_decompress_depth_in_place(struct si_context *sctx,
texture->dirty_level_mask &= ~(1 << level);
}
}
sctx->db_inplace_flush_enabled = false;
}
void si_flush_depth_textures(struct si_context *sctx,

7
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -49,12 +49,7 @@ static void si_destroy_context(struct pipe_context *context)
if (sctx->dummy_pixel_shader) {
sctx->b.b.delete_fs_state(&sctx->b.b, sctx->dummy_pixel_shader);
}
for (int i = 0; i < 8; i++) {
sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_depth_stencil[i]);
sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_depth[i]);
sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_stencil[i]);
}
sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush_inplace);
sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);

11
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -86,10 +86,7 @@ struct si_framebuffer {
struct si_context {
struct r600_common_context b;
struct blitter_context *blitter;
void *custom_dsa_flush_depth_stencil[8];
void *custom_dsa_flush_depth[8];
void *custom_dsa_flush_stencil[8];
void *custom_dsa_flush_inplace;
void *custom_dsa_flush;
void *custom_blend_resolve;
void *custom_blend_decompress;
void *custom_blend_fastclear;
@ -161,6 +158,12 @@ struct si_context {
/* SI state handling */
union si_state queued;
union si_state emitted;
/* Additional DB state. */
bool dbcb_depth_copy_enabled;
bool dbcb_stencil_copy_enabled;
unsigned dbcb_copy_sample;
bool db_inplace_flush_enabled;
};
/* si_blit.c */

35
src/gallium/drivers/radeonsi/si_state.c
View file

@ -757,7 +757,6 @@ static void *si_create_dsa_state(struct pipe_context *ctx,
struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
struct si_pm4_state *pm4 = &dsa->pm4;
unsigned db_depth_control;
unsigned db_render_control;
uint32_t db_stencil_control = 0;
if (dsa == NULL) {
@ -802,9 +801,7 @@ static void *si_create_dsa_state(struct pipe_context *ctx,
}
/* misc */
db_render_control = 0;
si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
return dsa;
@ -828,28 +825,11 @@ static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
}
static void *si_create_db_flush_dsa(struct si_context *sctx, bool copy_depth,
bool copy_stencil, int sample)
static void *si_create_db_flush_dsa(struct si_context *sctx)
{
struct pipe_depth_stencil_alpha_state dsa;
struct si_state_dsa *state;
struct pipe_depth_stencil_alpha_state dsa = {};
memset(&dsa, 0, sizeof(dsa));
state = sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
if (copy_depth || copy_stencil) {
si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
S_028000_DEPTH_COPY(copy_depth) |
S_028000_STENCIL_COPY(copy_stencil) |
S_028000_COPY_CENTROID(1) |
S_028000_COPY_SAMPLE(sample));
} else {
si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
S_028000_DEPTH_COMPRESS_DISABLE(1) |
S_028000_STENCIL_COMPRESS_DISABLE(1));
}
return state;
return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
}
/*
@ -2933,8 +2913,6 @@ static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
void si_init_state_functions(struct si_context *sctx)
{
int i;
si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state, 0);
sctx->b.b.create_blend_state = si_create_blend_state;
@ -2950,12 +2928,7 @@ void si_init_state_functions(struct si_context *sctx)
sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
for (i = 0; i < 8; i++) {
sctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(sctx, true, true, i);
sctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(sctx, true, false, i);
sctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(sctx, false, true, i);
}
sctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(sctx, false, false, 0);
sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);

16
src/gallium/drivers/radeonsi/si_state_draw.c
View file

@ -739,6 +739,22 @@ static void si_state_draw(struct si_context *sctx,
}
}
/* DB_RENDER_CONTROL */
if (sctx->dbcb_depth_copy_enabled ||
sctx->dbcb_stencil_copy_enabled) {
si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL,
S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
S_028000_COPY_CENTROID(1) |
S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
} else if (sctx->db_inplace_flush_enabled) {
si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL,
S_028000_DEPTH_COMPRESS_DISABLE(1) |
S_028000_STENCIL_COMPRESS_DISABLE(1));
} else {
si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, 0);
}
if (info->count_from_stream_output) {
struct r600_so_target *t =
(struct r600_so_target*)info->count_from_stream_output;