diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 01c7ad45caf..a54e793542b 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1663,7 +1663,6 @@ radv_GetMemoryFdKHR(VkDevice _device, const VkMemoryGetFdInfoKHR *pGetFdInfo, in
    if (memory->image) {
       struct radv_image *image = memory->image;
 
-      assert(memory->image->bindings[0].offset == 0);
       radv_image_bo_set_metadata(device, image, memory->bo);
    }
 
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 5ffc50ce3de..e841fab4d98 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -781,8 +781,7 @@ radv_image_bo_set_metadata(struct radv_device *device, struct radv_image *image,
       md.u.gfx12.dcc_write_compress_disable = surface->u.gfx9.color.dcc_write_compress_disable;
       md.u.gfx12.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
    } else if (pdev->info.gfx_level >= GFX9) {
-      uint64_t dcc_offset =
-         image->bindings[0].offset + (surface->display_dcc_offset ? surface->display_dcc_offset : surface->meta_offset);
+      const uint64_t dcc_offset = surface->display_dcc_offset ? surface->display_dcc_offset : surface->meta_offset;
       md.u.gfx9.swizzle_mode = surface->u.gfx9.swizzle_mode;
       md.u.gfx9.dcc_offset_256b = dcc_offset >> 8;
       md.u.gfx9.dcc_pitch_max = surface->u.gfx9.color.display_dcc_pitch_max;