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ac/shader: move scanning some info about input PS declarations
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
parent
e207b2e2c8
commit
639c4f2b54
5 changed files with 26 additions and 15 deletions
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@ -5638,12 +5638,6 @@ handle_fs_inputs(struct radv_shader_context *ctx,
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}
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}
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ctx->shader_info->fs.num_interp = index;
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if (ctx->input_mask & (1 << VARYING_SLOT_PNTC))
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ctx->shader_info->fs.has_pcoord = true;
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if (ctx->input_mask & (1 << VARYING_SLOT_PRIMITIVE_ID))
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ctx->shader_info->fs.prim_id_input = true;
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if (ctx->input_mask & (1 << VARYING_SLOT_LAYER))
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ctx->shader_info->fs.layer_input = true;
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ctx->shader_info->fs.input_mask = ctx->input_mask >> VARYING_SLOT_VAR0;
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if (ctx->shader_info->info.needs_multiview_view_index)
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@ -177,11 +177,8 @@ struct ac_shader_variant_info {
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unsigned num_interp;
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uint32_t input_mask;
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uint32_t flat_shaded_mask;
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bool has_pcoord;
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bool can_discard;
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bool early_fragment_test;
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bool prim_id_input;
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bool layer_input;
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} fs;
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struct {
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unsigned block_size[3];
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@ -194,6 +194,21 @@ gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var,
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struct ac_shader_info *info)
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{
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const struct glsl_type *type = glsl_without_array(var->type);
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int idx = var->data.location;
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switch (idx) {
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case VARYING_SLOT_PNTC:
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info->ps.has_pcoord = true;
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break;
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case VARYING_SLOT_PRIMITIVE_ID:
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info->ps.prim_id_input = true;
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break;
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case VARYING_SLOT_LAYER:
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info->ps.layer_input = true;
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break;
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default:
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break;
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}
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if (glsl_get_base_type(type) == GLSL_TYPE_FLOAT) {
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if (var->data.sample)
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@ -49,6 +49,9 @@ struct ac_shader_info {
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bool writes_z;
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bool writes_stencil;
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bool writes_sample_mask;
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bool has_pcoord;
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bool prim_id_input;
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bool layer_input;
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} ps;
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struct {
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bool uses_grid_size;
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@ -1779,9 +1779,9 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
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/* TODO: These are no longer used as keys we should refactor this */
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keys[MESA_SHADER_VERTEX].vs.export_prim_id =
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pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
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pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
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keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =
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pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input;
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pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
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}
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if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
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@ -2750,7 +2750,7 @@ radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
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unsigned ps_offset = 0;
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if (ps->info.fs.prim_id_input) {
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if (ps->info.info.ps.prim_id_input) {
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unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
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if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
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ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
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@ -2758,7 +2758,9 @@ radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
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}
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}
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if (ps->info.fs.layer_input) {
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if (ps->info.info.ps.layer_input ||
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ps->info.info.ps.uses_input_attachments ||
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ps->info.info.needs_multiview_view_index) {
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unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
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if (vs_offset != AC_EXP_PARAM_UNDEFINED)
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ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true);
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@ -2767,7 +2769,7 @@ radv_pipeline_generate_ps_inputs(struct radeon_winsys_cs *cs,
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++ps_offset;
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}
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if (ps->info.fs.has_pcoord) {
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if (ps->info.info.ps.has_pcoord) {
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unsigned val;
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val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
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ps_input_cntl[ps_offset] = val;
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@ -3026,7 +3028,7 @@ radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
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}
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ia_multi_vgt_param.ia_switch_on_eoi = false;
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if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.fs.prim_id_input)
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if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input)
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ia_multi_vgt_param.ia_switch_on_eoi = true;
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if (radv_pipeline_has_gs(pipeline) &&
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pipeline->shaders[MESA_SHADER_GEOMETRY]->info.info.uses_prim_id)
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