From 637f618ac5c46c2813645fc5279e89bfc768c280 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 18 Aug 2025 11:11:30 +0200 Subject: [PATCH] radeonsi: Flush L2 for render condition when CP can't use L2 If CP can't use L2 then it also can't read the render condition through L2, so we need a flush, just like on GFX6-8. Cc: mesa-stable Part-of: --- src/gallium/drivers/radeonsi/si_query.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_query.c b/src/gallium/drivers/radeonsi/si_query.c index d2224c88abe..8c1cc5a44d8 100644 --- a/src/gallium/drivers/radeonsi/si_query.c +++ b/src/gallium/drivers/radeonsi/si_query.c @@ -1696,7 +1696,7 @@ static void si_render_condition(struct pipe_context *ctx, struct pipe_query *que /* Settings this in the render cond atom is too late, * so set it here. */ - if (sctx->gfx_level <= GFX8) { + if (sctx->gfx_level <= GFX8 || sctx->screen->info.cp_sdma_ge_use_system_memory_scope) { sctx->barrier_flags |= SI_BARRIER_WB_L2 | SI_BARRIER_PFP_SYNC_ME; si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier); }