diff --git a/src/gallium/drivers/iris/iris_context.h b/src/gallium/drivers/iris/iris_context.h index 27c02d8ae88..4ba5c79c0b6 100644 --- a/src/gallium/drivers/iris/iris_context.h +++ b/src/gallium/drivers/iris/iris_context.h @@ -47,6 +47,9 @@ struct iris_context; struct blorp_batch; struct blorp_params; +#define IRIS_MAX_DRAW_BUFFERS 8 +#define IRIS_MAX_SOL_BINDINGS 64 + #define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27) /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */ #define IRIS_MAX_ABOS 16 @@ -1032,7 +1035,7 @@ struct iris_context { * Array of aux usages for drawing, altered to account for any * self-dependencies from resources bound for sampling and rendering. */ - enum isl_aux_usage draw_aux_usage[BRW_MAX_DRAW_BUFFERS]; + enum isl_aux_usage draw_aux_usage[IRIS_MAX_DRAW_BUFFERS]; /** Aux usage of the fb's depth buffer (which may or may not exist). */ enum isl_aux_usage hiz_usage; diff --git a/src/gallium/drivers/iris/iris_draw.c b/src/gallium/drivers/iris/iris_draw.c index c59ce07132a..d59ebd8b570 100644 --- a/src/gallium/drivers/iris/iris_draw.c +++ b/src/gallium/drivers/iris/iris_draw.c @@ -309,7 +309,7 @@ iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info, iris_update_compiled_shaders(ice); if (ice->state.dirty & IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES) { - bool draw_aux_buffer_disabled[BRW_MAX_DRAW_BUFFERS] = { }; + bool draw_aux_buffer_disabled[IRIS_MAX_DRAW_BUFFERS] = { }; for (gl_shader_stage stage = 0; stage < MESA_SHADER_COMPUTE; stage++) { if (ice->shaders.prog[stage]) iris_predraw_resolve_inputs(ice, batch, draw_aux_buffer_disabled, diff --git a/src/gallium/drivers/iris/iris_program.c b/src/gallium/drivers/iris/iris_program.c index 03349e0e7e0..d7d323dc3a5 100644 --- a/src/gallium/drivers/iris/iris_program.c +++ b/src/gallium/drivers/iris/iris_program.c @@ -3128,7 +3128,7 @@ iris_bind_fs_state(struct pipe_context *ctx, void *state) const unsigned color_bits = BITFIELD64_BIT(FRAG_RESULT_COLOR) | - BITFIELD64_RANGE(FRAG_RESULT_DATA0, BRW_MAX_DRAW_BUFFERS); + BITFIELD64_RANGE(FRAG_RESULT_DATA0, IRIS_MAX_DRAW_BUFFERS); /* Fragment shader outputs influence HasWriteableRT */ if (!old_ish || !new_ish || @@ -3314,6 +3314,9 @@ iris_shader_perf_log(void *data, unsigned *id, const char *fmt, ...) void iris_compiler_init(struct iris_screen *screen) { + STATIC_ASSERT(IRIS_MAX_DRAW_BUFFERS == BRW_MAX_DRAW_BUFFERS); + STATIC_ASSERT(IRIS_MAX_SOL_BINDINGS == BRW_MAX_SOL_BINDINGS); + screen->compiler = brw_compiler_create(screen, screen->devinfo); screen->compiler->shader_debug_log = iris_shader_debug_log; screen->compiler->shader_perf_log = iris_shader_perf_log; diff --git a/src/gallium/drivers/iris/iris_screen.c b/src/gallium/drivers/iris/iris_screen.c index df19633f358..07299681cea 100644 --- a/src/gallium/drivers/iris/iris_screen.c +++ b/src/gallium/drivers/iris/iris_screen.c @@ -54,7 +54,6 @@ #include "iris_resource.h" #include "iris_screen.h" #include "compiler/glsl_types.h" -#include "intel/compiler/brw_compiler.h" #include "intel/common/intel_gem.h" #include "intel/common/intel_l3_config.h" #include "intel/common/intel_uuid.h" @@ -309,7 +308,7 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_PREFER_BACK_BUFFER_REUSE: return false; case PIPE_CAP_FBFETCH: - return BRW_MAX_DRAW_BUFFERS; + return IRIS_MAX_DRAW_BUFFERS; case PIPE_CAP_FBFETCH_COHERENT: case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE: case PIPE_CAP_POST_DEPTH_COVERAGE: @@ -323,7 +322,7 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: return 1; case PIPE_CAP_MAX_RENDER_TARGETS: - return BRW_MAX_DRAW_BUFFERS; + return IRIS_MAX_DRAW_BUFFERS; case PIPE_CAP_MAX_TEXTURE_2D_SIZE: return 16384; case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: @@ -335,9 +334,9 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: return 2048; case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: - return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS; + return IRIS_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS; case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: - return BRW_MAX_SOL_BINDINGS; + return IRIS_MAX_SOL_BINDINGS; case PIPE_CAP_GLSL_FEATURE_LEVEL: case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY: return 460; diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index c5dc1e888e6..27edbf6587c 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -1561,7 +1561,7 @@ struct iris_blend_state { /** Partial BLEND_STATE */ uint32_t blend_state[GENX(BLEND_STATE_length) + - BRW_MAX_DRAW_BUFFERS * GENX(BLEND_STATE_ENTRY_length)]; + IRIS_MAX_DRAW_BUFFERS * GENX(BLEND_STATE_ENTRY_length)]; bool alpha_to_coverage; /* for shader key */ @@ -1574,8 +1574,8 @@ struct iris_blend_state { /** Does RT[0] use dual color blending? */ bool dual_color_blending; - int ps_dst_blend_factor[BRW_MAX_DRAW_BUFFERS]; - int ps_dst_alpha_blend_factor[BRW_MAX_DRAW_BUFFERS]; + int ps_dst_blend_factor[IRIS_MAX_DRAW_BUFFERS]; + int ps_dst_alpha_blend_factor[IRIS_MAX_DRAW_BUFFERS]; }; static enum pipe_blendfactor @@ -1606,13 +1606,13 @@ iris_create_blend_state(struct pipe_context *ctx, cso->blend_enables = 0; cso->color_write_enables = 0; - STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS <= 8); + STATIC_ASSERT(IRIS_MAX_DRAW_BUFFERS <= 8); cso->alpha_to_coverage = state->alpha_to_coverage; bool indep_alpha_blend = false; - for (int i = 0; i < BRW_MAX_DRAW_BUFFERS; i++) { + for (int i = 0; i < IRIS_MAX_DRAW_BUFFERS; i++) { const struct pipe_rt_blend_state *rt = &state->rt[state->independent_blend_enable ? i : 0]; @@ -1732,7 +1732,7 @@ has_writeable_rt(const struct iris_blend_state *cso_blend, unsigned rt_outputs = fs_info->outputs_written >> FRAG_RESULT_DATA0; if (fs_info->outputs_written & BITFIELD64_BIT(FRAG_RESULT_COLOR)) - rt_outputs = (1 << BRW_MAX_DRAW_BUFFERS) - 1; + rt_outputs = (1 << IRIS_MAX_DRAW_BUFFERS) - 1; return cso_blend->color_write_enables & rt_outputs; }