From 634925694da0d2fc8a51fd30b96cba8d044bdcac Mon Sep 17 00:00:00 2001
From: Sagar Ghuge <sagar.ghuge@intel.com>
Date: Tue, 4 Aug 2020 23:04:52 -0700
Subject: [PATCH] intel/disasm: Disassemble LSC message extended descriptors

v2 (Mark Janes):
 - changed to lsc convention

v3 (Jason Ekstrand):
 - Use lsc_msg_desc_addr_type

Co-authored-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11600>
---
 src/intel/compiler/brw_disasm.c | 62 +++++++++++++++++++++++++++++----
 1 file changed, 55 insertions(+), 7 deletions(-)

diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c
index 848aea16dc7..84b1c7c9e77 100644
--- a/src/intel/compiler/brw_disasm.c
+++ b/src/intel/compiler/brw_disasm.c
@@ -1825,6 +1825,50 @@ write_label(FILE *file, const struct intel_device_info *devinfo,
    }
 }
 
+static void
+lsc_disassemble_ex_desc(const struct intel_device_info *devinfo,
+                        uint32_t imm_desc,
+                        uint32_t imm_ex_desc,
+                        FILE *file)
+{
+   const unsigned addr_type = lsc_msg_desc_addr_type(devinfo, imm_desc);
+   switch (addr_type) {
+   case LSC_ADDR_SURFTYPE_FLAT:
+      format(file, "base_offset %u ",
+             lsc_flat_ex_desc_base_offset(devinfo, imm_ex_desc));
+      break;
+   case LSC_ADDR_SURFTYPE_BSS:
+   case LSC_ADDR_SURFTYPE_SS:
+      format(file, "surface_state_index %u ",
+             lsc_bss_ex_desc_index(devinfo, imm_ex_desc));
+      break;
+   case LSC_ADDR_SURFTYPE_BTI:
+      format(file, "BTI %u ",
+             lsc_bti_ex_desc_index(devinfo, imm_ex_desc));
+      format(file, "base_offset %u ",
+             lsc_bti_ex_desc_base_offset(devinfo, imm_ex_desc));
+      break;
+   default:
+      format(file, "unsupported address surface type %d", addr_type);
+      break;
+   }
+}
+
+static inline bool
+brw_sfid_is_lsc(unsigned sfid)
+{
+   switch (sfid) {
+   case GFX12_SFID_UGM:
+   case GFX12_SFID_SLM:
+   case GFX12_SFID_TGM:
+      return true;
+   default:
+      break;
+   }
+
+   return false;
+}
+
 int
 brw_disassemble_inst(FILE *file, const struct intel_device_info *devinfo,
                      const brw_inst *inst, bool is_compacted,
@@ -2370,14 +2414,18 @@ brw_disassemble_inst(FILE *file, const struct intel_device_info *devinfo,
          if (space)
             string(file, " ");
       }
-      if (has_imm_desc)
-         format(file, "mlen %u", brw_message_desc_mlen(devinfo, imm_desc));
-      if (has_imm_ex_desc) {
-         format(file, " ex_mlen %u",
-                brw_message_ex_desc_ex_mlen(devinfo, imm_ex_desc));
+      if (brw_sfid_is_lsc(sfid)) {
+            lsc_disassemble_ex_desc(devinfo, imm_desc, imm_ex_desc, file);
+      } else {
+         if (has_imm_desc)
+            format(file, "mlen %u", brw_message_desc_mlen(devinfo, imm_desc));
+         if (has_imm_ex_desc) {
+            format(file, " ex_mlen %u",
+                   brw_message_ex_desc_ex_mlen(devinfo, imm_ex_desc));
+         }
+         if (has_imm_desc)
+            format(file, " rlen %u", brw_message_desc_rlen(devinfo, imm_desc));
       }
-      if (has_imm_desc)
-         format(file, " rlen %u", brw_message_desc_rlen(devinfo, imm_desc));
    }
    pad(file, 64);
    if (opcode != BRW_OPCODE_NOP && opcode != BRW_OPCODE_NENOP) {