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st/radeonsi: enable uniform packing in NIR backend
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
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parent
231333a20d
commit
632d5e97ef
2 changed files with 7 additions and 9 deletions
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@ -251,6 +251,11 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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return RADEON_SPARSE_PAGE_SIZE;
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return 0;
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case PIPE_CAP_PACKED_UNIFORMS:
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if (sscreen->debug_flags & DBG(NIR))
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return 1;
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return 0;
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/* Unsupported features. */
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case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
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case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
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@ -269,7 +274,6 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_TILE_RASTER_ORDER:
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case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
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case PIPE_CAP_CONTEXT_PRIORITY_MASK:
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case PIPE_CAP_PACKED_UNIFORMS:
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return 0;
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case PIPE_CAP_FENCE_SIGNAL:
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@ -753,14 +753,8 @@ st_finalize_nir(struct st_context *st, struct gl_program *prog,
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st_nir_assign_uniform_locations(st->ctx, prog, shader_program,
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&nir->uniforms, &nir->num_uniforms);
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/* Below is a quick hack so that uniform lowering only runs on radeonsi
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* (the only NIR backend that currently supports tess) once we enable
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* uniform packing support we will just use
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* ctx->Const.PackedDriverUniformStorage for this check.
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*/
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if (screen->get_shader_param(screen, PIPE_SHADER_TESS_CTRL,
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PIPE_SHADER_CAP_MAX_INSTRUCTIONS) > 0) {
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NIR_PASS_V(nir, nir_lower_io, nir_var_uniform, type_size,
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if (st->ctx->Const.PackedDriverUniformStorage) {
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NIR_PASS_V(nir, nir_lower_io, nir_var_uniform, st_glsl_type_dword_size,
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(nir_lower_io_options)0);
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NIR_PASS_V(nir, st_nir_lower_uniforms_to_ubo, prog->Parameters);
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}
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