st/radeonsi: enable uniform packing in NIR backend

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Timothy Arceri 2018-03-14 09:51:23 +11:00
parent 231333a20d
commit 632d5e97ef
2 changed files with 7 additions and 9 deletions

View file

@ -251,6 +251,11 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return RADEON_SPARSE_PAGE_SIZE;
return 0;
case PIPE_CAP_PACKED_UNIFORMS:
if (sscreen->debug_flags & DBG(NIR))
return 1;
return 0;
/* Unsupported features. */
case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
@ -269,7 +274,6 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_TILE_RASTER_ORDER:
case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
case PIPE_CAP_CONTEXT_PRIORITY_MASK:
case PIPE_CAP_PACKED_UNIFORMS:
return 0;
case PIPE_CAP_FENCE_SIGNAL:

View file

@ -753,14 +753,8 @@ st_finalize_nir(struct st_context *st, struct gl_program *prog,
st_nir_assign_uniform_locations(st->ctx, prog, shader_program,
&nir->uniforms, &nir->num_uniforms);
/* Below is a quick hack so that uniform lowering only runs on radeonsi
* (the only NIR backend that currently supports tess) once we enable
* uniform packing support we will just use
* ctx->Const.PackedDriverUniformStorage for this check.
*/
if (screen->get_shader_param(screen, PIPE_SHADER_TESS_CTRL,
PIPE_SHADER_CAP_MAX_INSTRUCTIONS) > 0) {
NIR_PASS_V(nir, nir_lower_io, nir_var_uniform, type_size,
if (st->ctx->Const.PackedDriverUniformStorage) {
NIR_PASS_V(nir, nir_lower_io, nir_var_uniform, st_glsl_type_dword_size,
(nir_lower_io_options)0);
NIR_PASS_V(nir, st_nir_lower_uniforms_to_ubo, prog->Parameters);
}