diff --git a/src/nouveau/compiler/nak/calc_instr_deps.rs b/src/nouveau/compiler/nak/calc_instr_deps.rs
index 0824fe855d9..cb1804f48c5 100644
--- a/src/nouveau/compiler/nak/calc_instr_deps.rs
+++ b/src/nouveau/compiler/nak/calc_instr_deps.rs
@@ -13,6 +13,7 @@ struct RegTracker<T> {
     ureg: [T; 63],
     pred: [T; 7],
     upred: [T; 7],
+    carry: [T; 1],
 }
 
 impl<T: Copy> RegTracker<T> {
@@ -22,6 +23,7 @@ impl<T: Copy> RegTracker<T> {
             ureg: [v; 63],
             pred: [v; 7],
             upred: [v; 7],
+            carry: [v; 1],
         }
     }
 
@@ -74,6 +76,7 @@ impl<T> Index<RegRef> for RegTracker<T> {
             RegFile::UGPR => &self.ureg[range],
             RegFile::Pred => &self.pred[range],
             RegFile::UPred => &self.upred[range],
+            RegFile::Carry => &self.carry[range],
             RegFile::Bar => &[], // Barriers have a HW scoreboard
             RegFile::Mem => panic!("Not a register"),
         }
@@ -93,6 +96,7 @@ impl<T> IndexMut<RegRef> for RegTracker<T> {
             RegFile::UGPR => &mut self.ureg[range],
             RegFile::Pred => &mut self.pred[range],
             RegFile::UPred => &mut self.upred[range],
+            RegFile::Carry => &mut self.carry[range],
             RegFile::Bar => &mut [], // Barriers have a HW scoreboard
             RegFile::Mem => panic!("Not a register"),
         }
diff --git a/src/nouveau/compiler/nak/encode_sm50.rs b/src/nouveau/compiler/nak/encode_sm50.rs
index 24d75177e51..fb54e0159d3 100644
--- a/src/nouveau/compiler/nak/encode_sm50.rs
+++ b/src/nouveau/compiler/nak/encode_sm50.rs
@@ -3,8 +3,8 @@
  * SPDX-License-Identifier: MIT
  */
 
-use bitview::*;
 use crate::ir::*;
+use bitview::*;
 
 use std::collections::HashMap;
 use std::ops::Range;
diff --git a/src/nouveau/compiler/nak/ir.rs b/src/nouveau/compiler/nak/ir.rs
index 20288c4423f..b38f1d9938f 100644
--- a/src/nouveau/compiler/nak/ir.rs
+++ b/src/nouveau/compiler/nak/ir.rs
@@ -72,25 +72,37 @@ pub enum RegFile {
     /// Uniform predicate registers are 1 bit and uniform across a wave.
     UPred = 3,
 
+    /// The carry flag register file
+    ///
+    /// Only one carry flag register exists in hardware, but representing it as
+    /// a reg file simplifies dependency tracking.
+    ///
+    /// This is used only on SM50.
+    Carry = 4,
+
     /// The barrier register file
     ///
     /// This is a lane mask used for wave re-convergence instructions.
-    Bar = 4,
+    Bar = 5,
 
     /// The memory register file
     ///
     /// This is a virtual register file for things which will get spilled to
     /// local memory.  Each memory location is 32 bits per SIMT channel.
-    Mem = 5,
+    Mem = 6,
 }
 
-const NUM_REG_FILES: usize = 6;
+const NUM_REG_FILES: usize = 7;
 
 impl RegFile {
     /// Returns true if the register file is uniform across a wave
     pub fn is_uniform(&self) -> bool {
         match self {
-            RegFile::GPR | RegFile::Pred | RegFile::Bar | RegFile::Mem => false,
+            RegFile::GPR
+            | RegFile::Pred
+            | RegFile::Carry
+            | RegFile::Bar
+            | RegFile::Mem => false,
             RegFile::UGPR | RegFile::UPred => true,
         }
     }
@@ -99,16 +111,22 @@ impl RegFile {
     pub fn is_gpr(&self) -> bool {
         match self {
             RegFile::GPR | RegFile::UGPR => true,
-            RegFile::Pred | RegFile::UPred | RegFile::Bar | RegFile::Mem => {
-                false
-            }
+            RegFile::Pred
+            | RegFile::UPred
+            | RegFile::Carry
+            | RegFile::Bar
+            | RegFile::Mem => false,
         }
     }
 
     /// Returns true if the register file is a predicate register file
     pub fn is_predicate(&self) -> bool {
         match self {
-            RegFile::GPR | RegFile::UGPR | RegFile::Bar | RegFile::Mem => false,
+            RegFile::GPR
+            | RegFile::UGPR
+            | RegFile::Carry
+            | RegFile::Bar
+            | RegFile::Mem => false,
             RegFile::Pred | RegFile::UPred => true,
         }
     }
@@ -143,6 +161,13 @@ impl RegFile {
                     0
                 }
             }
+            RegFile::Carry => {
+                if sm >= 70 {
+                    0
+                } else {
+                    1
+                }
+            }
             RegFile::Bar => {
                 if sm >= 70 {
                     16
@@ -160,6 +185,7 @@ impl RegFile {
             RegFile::UGPR => "ur",
             RegFile::Pred => "p",
             RegFile::UPred => "up",
+            RegFile::Carry => "c",
             RegFile::Bar => "b",
             RegFile::Mem => "m",
         }
@@ -173,6 +199,7 @@ impl fmt::Display for RegFile {
             RegFile::UGPR => write!(f, "UGPR"),
             RegFile::Pred => write!(f, "Pred"),
             RegFile::UPred => write!(f, "UPred"),
+            RegFile::Carry => write!(f, "Carry"),
             RegFile::Bar => write!(f, "Bar"),
             RegFile::Mem => write!(f, "Mem"),
         }
@@ -194,8 +221,9 @@ impl TryFrom<u32> for RegFile {
             1 => Ok(RegFile::UGPR),
             2 => Ok(RegFile::Pred),
             3 => Ok(RegFile::UPred),
-            4 => Ok(RegFile::Bar),
-            5 => Ok(RegFile::Mem),
+            4 => Ok(RegFile::Carry),
+            5 => Ok(RegFile::Bar),
+            6 => Ok(RegFile::Mem),
             _ => Err("Invalid register file number"),
         }
     }
@@ -316,6 +344,7 @@ impl<T> PerRegFile<T> {
                 f(RegFile::UGPR),
                 f(RegFile::Pred),
                 f(RegFile::UPred),
+                f(RegFile::Carry),
                 f(RegFile::Bar),
                 f(RegFile::Mem),
             ],
@@ -587,6 +616,7 @@ impl RegRef {
             RegFile::UGPR => 63,
             RegFile::Pred => 7,
             RegFile::UPred => 7,
+            RegFile::Carry => panic!("Carry has no zero index"),
             RegFile::Bar => panic!("Bar has no zero index"),
             RegFile::Mem => panic!("Mem has no zero index"),
         }
diff --git a/src/nouveau/compiler/nak/opt_lop.rs b/src/nouveau/compiler/nak/opt_lop.rs
index 3b0e395ab00..fb508989455 100644
--- a/src/nouveau/compiler/nak/opt_lop.rs
+++ b/src/nouveau/compiler/nak/opt_lop.rs
@@ -170,7 +170,9 @@ impl LopPass {
             srcs[src_idx] = match ssa.file() {
                 RegFile::GPR | RegFile::UGPR => SrcRef::Zero.into(),
                 RegFile::Pred | RegFile::UPred => SrcRef::True.into(),
-                RegFile::Bar | RegFile::Mem => panic!("Not a normal register"),
+                RegFile::Carry | RegFile::Bar | RegFile::Mem => {
+                    panic!("Not a normal register");
+                }
             };
 
             for i in 0..3 {