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anv: set depth stall enabled when depth flush enabled on gen12

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This implements HW workaround #1409600907 for anv driver.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3378>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3378>
This commit is contained in:
Tapani Pälli 2020-01-14 10:03:21 +02:00
parent 3cec148455
commit 630cbb45ac
2 changed files with 19 additions and 0 deletions
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5
src/intel/vulkan/gen8_cmd_buffer.c
View file

@ -142,6 +142,11 @@ genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable)
pc.RenderTargetCacheFlushEnable = true;
#if GEN_GEN >= 12
pc.TileCacheFlushEnable = true;
/* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
* be set with any PIPE_CONTROL with Depth Flush Enable bit set.
*/
pc.DepthStallEnable = true;
#endif
}

14
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -1904,7 +1904,16 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
pipe.RenderTargetCacheFlushEnable =
bits & ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
/* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
* be set with any PIPE_CONTROL with Depth Flush Enable bit set.
*/
#if GEN_GEN >= 12
pipe.DepthStallEnable =
pipe.DepthCacheFlushEnable || (bits & ANV_PIPE_DEPTH_STALL_BIT);
#else
pipe.DepthStallEnable = bits & ANV_PIPE_DEPTH_STALL_BIT;
#endif
pipe.CommandStreamerStallEnable = bits & ANV_PIPE_CS_STALL_BIT;
pipe.StallAtPixelScoreboard = bits & ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
@ -4107,6 +4116,11 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
pc.CommandStreamerStallEnable = true;
#if GEN_GEN >= 12
pc.TileCacheFlushEnable = true;
/* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must be
* set with any PIPE_CONTROL with Depth Flush Enable bit set.
*/
pc.DepthStallEnable = true;
#endif
}