From 630a4d2249f0c359598cacef2b12dac554ec417f Mon Sep 17 00:00:00 2001
From: David Rosca <david.rosca@amd.com>
Date: Mon, 27 Apr 2026 15:28:02 +0200
Subject: [PATCH] radeonsi: Always use 2D tiling for video dpb

Fixes decode on VCN5 with AMD_DEBUG=notiling

Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41201>
---
 src/gallium/drivers/radeonsi/si_texture.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index 2e764e4b593..1f1ea4e040a 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -1389,6 +1389,10 @@ static enum radeon_surf_mode si_choose_tiling(struct si_screen *sscreen,
    if (sscreen->info.gfx_level == GFX8 && tc_compatible_htile)
       return RADEON_SURF_MODE_2D;
 
+   /* Video DPB must be 2D tiled. */
+   if (templ->bind & (PIPE_BIND_VIDEO_DECODE_DPB | PIPE_BIND_VIDEO_ENCODE_DPB))
+      return RADEON_SURF_MODE_2D;
+
    /* Handle common candidates for the linear mode.
     * Compressed textures and DB surfaces must always be tiled.
     */