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radeonsi: fix assert triggered on gfx6 after the tessellation update
This change updates the affected calls to the proper function which is radeon_set_config_reg(). For instance, this issue is triggered with "piglit/bin/textureSize tes isampler2DMSArray -auto -fbo": vertex-program-two-side: ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:4981: void si_emit_spi_ge_ring_state(si_context*, unsigned int): Assertion `(0x008988) >= CIK_UCONFIG_REG_OFFSET && (0x008988) < CIK_UCONFIG_REG_END' failed. Fixes:bd71d62b8f("radeonsi: program tessellation rings right before draws") Signed-off-by: Patrick Lerda <patrick9876@free.fr> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29645> (cherry picked from commit301a3bacce)
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9d647a15c9
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2 changed files with 4 additions and 4 deletions
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@ -3304,7 +3304,7 @@
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"description": "radeonsi: fix assert triggered on gfx6 after the tessellation update",
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"nominated": true,
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"nomination_type": 1,
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"resolution": 0,
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"resolution": 1,
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"main_sha": null,
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"because_sha": "bd71d62b8fcf0c74ba31415375a0ec68b0525c88",
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"notes": null
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@ -4747,9 +4747,9 @@ static void si_emit_spi_ge_ring_state(struct si_context *sctx, unsigned index)
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else if (sctx->gfx_level == GFX9)
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radeon_set_uconfig_reg(R_030944_VGT_TF_MEMORY_BASE_HI, S_030944_BASE_HI(factor_va >> 40));
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} else {
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radeon_set_uconfig_reg(R_008988_VGT_TF_RING_SIZE, S_008988_SIZE(tf_ring_size_field));
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radeon_set_uconfig_reg(R_0089B8_VGT_TF_MEMORY_BASE, factor_va >> 8);
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radeon_set_uconfig_reg(R_0089B0_VGT_HS_OFFCHIP_PARAM, sscreen->hs.hs_offchip_param);
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radeon_set_config_reg(R_008988_VGT_TF_RING_SIZE, S_008988_SIZE(tf_ring_size_field));
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radeon_set_config_reg(R_0089B8_VGT_TF_MEMORY_BASE, factor_va >> 8);
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radeon_set_config_reg(R_0089B0_VGT_HS_OFFCHIP_PARAM, sscreen->hs.hs_offchip_param);
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}
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radeon_end();
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}
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