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freedreno/devices: Unify magic_regs for A740 and A32

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The only difference was RB_UNKNOWN_8E01 being set to 0x0 or 0x00000000.
Their raw_magic_regs however are different.

Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31328>
(cherry picked from commit dde6acceb5)
This commit is contained in:
Valentine Burley 2024-09-19 14:07:37 +00:00 • committed by Eric Engestrom
parent c282a40403
commit 6293074106
2 changed files with 23 additions and 39 deletions
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2
.pick_status.json
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@ -14674,7 +14674,7 @@
"description": "freedreno/devices: Unify magic_regs for A740 and A32",
"nominated": false,
"nomination_type": 3,
"resolution": 4,
"resolution": 1,
"main_sha": null,
"because_sha": null,
"notes": null

60
src/freedreno/common/freedreno_devices.py
View file

@ -941,6 +941,26 @@ a730_raw_magic_regs = [
[A6XXRegs.REG_A7XX_GRAS_UNKNOWN_80F4, 0x00000000],
]
a740_magic_regs = dict(
# PC_POWER_CNTL = 7,
TPL1_DBG_ECO_CNTL = 0x11100000,
GRAS_DBG_ECO_CNTL = 0x00004800,
SP_CHICKEN_BITS = 0x10001400,
UCHE_CLIENT_PF = 0x00000084,
# Blob uses 0x1f or 0x1f1f, however these values cause vertices
# corruption in some tests.
PC_MODE_CNTL = 0x0000003f,
SP_DBG_ECO_CNTL = 0x10000000,
RB_DBG_ECO_CNTL = 0x00000000,
RB_DBG_ECO_CNTL_blit = 0x00000000, # is it even needed?
# HLSQ_DBG_ECO_CNTL = 0x0,
RB_UNKNOWN_8E01 = 0x0,
VPC_DBG_ECO_CNTL = 0x02000000,
UCHE_UNKNOWN_0E12 = 0x00000000,
RB_UNKNOWN_8E06 = 0x02080000,
)
a740_raw_magic_regs = [
[A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00040004],
[A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00040724],
@ -1044,25 +1064,7 @@ add_gpus([
cs_shared_mem_size = 32 * 1024,
wave_granularity = 2,
fibers_per_sp = 128 * 2 * 16,
magic_regs = dict(
# PC_POWER_CNTL = 7,
TPL1_DBG_ECO_CNTL = 0x11100000,
GRAS_DBG_ECO_CNTL = 0x00004800,
SP_CHICKEN_BITS = 0x10001400,
UCHE_CLIENT_PF = 0x00000084,
# Blob uses 0x1f or 0x1f1f, however these values cause vertices
# corruption in some tests.
PC_MODE_CNTL = 0x0000003f,
SP_DBG_ECO_CNTL = 0x10000000,
RB_DBG_ECO_CNTL = 0x00000000,
RB_DBG_ECO_CNTL_blit = 0x00000000, # is it even needed?
# HLSQ_DBG_ECO_CNTL = 0x0,
RB_UNKNOWN_8E01 = 0x0,
VPC_DBG_ECO_CNTL = 0x02000000,
UCHE_UNKNOWN_0E12 = 0x00000000,
RB_UNKNOWN_8E06 = 0x02080000,
),
magic_regs = a740_magic_regs,
raw_magic_regs = a740_raw_magic_regs,
))
@ -1080,25 +1082,7 @@ add_gpus([
cs_shared_mem_size = 32 * 1024,
wave_granularity = 2,
fibers_per_sp = 128 * 2 * 16,
magic_regs = dict(
# PC_POWER_CNTL = 7,
TPL1_DBG_ECO_CNTL = 0x11100000,
GRAS_DBG_ECO_CNTL = 0x00004800,
SP_CHICKEN_BITS = 0x10001400,
UCHE_CLIENT_PF = 0x00000084,
# Blob uses 0x1f or 0x1f1f, however these values cause vertices
# corruption in some tests.
PC_MODE_CNTL = 0x0000003f,
SP_DBG_ECO_CNTL = 0x10000000,
RB_DBG_ECO_CNTL = 0x00000000,
RB_DBG_ECO_CNTL_blit = 0x00000000, # is it even needed?
# HLSQ_DBG_ECO_CNTL = 0x0,
RB_UNKNOWN_8E01 = 0x00000000,
VPC_DBG_ECO_CNTL = 0x02000000,
UCHE_UNKNOWN_0E12 = 0x00000000,
RB_UNKNOWN_8E06 = 0x02080000,
),
magic_regs = a740_magic_regs,
raw_magic_regs = [
[A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00040004],
[A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000700],