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radeonsi/vce: Use radeon_bitstream functions to code headers

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Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38260>
This commit is contained in:
David Rosca 2025-11-05 14:59:59 +01:00 • committed by Marge Bot
parent 332ec608ad
commit 628694c16c
1 changed files with 12 additions and 131 deletions
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143
src/gallium/drivers/radeonsi/radeon_vce.c
View file

@ -674,146 +674,27 @@ static void session(struct rvce_encoder *enc)
static unsigned int write_sps(struct rvce_encoder *enc, uint8_t nal_byte, uint8_t *out)
{
struct pipe_h264_enc_seq_param *sps = &enc->pic.seq;
struct pipe_h264_enc_seq_param sps = enc->pic.seq;
sps.log2_max_frame_num_minus4 = 3;
struct radeon_bitstream bs;
radeon_bs_reset(&bs, out, NULL);
radeon_bs_set_emulation_prevention(&bs, false);
radeon_bs_code_fixed_bits(&bs, 0x00000001, 32);
radeon_bs_code_fixed_bits(&bs, nal_byte, 8);
radeon_bs_set_emulation_prevention(&bs, true);
radeon_bs_code_fixed_bits(&bs, sps->profile_idc, 8);
radeon_bs_code_fixed_bits(&bs, sps->enc_constraint_set_flags, 6);
radeon_bs_code_fixed_bits(&bs, 0x0, 2); /* reserved_zero_2bits */
radeon_bs_code_fixed_bits(&bs, sps->level_idc, 8);
radeon_bs_code_ue(&bs, 0x0); /* seq_parameter_set_id */
if (sps->profile_idc == 100 || sps->profile_idc == 110 ||
sps->profile_idc == 122 || sps->profile_idc == 244 ||
sps->profile_idc == 44 || sps->profile_idc == 83 ||
sps->profile_idc == 86 || sps->profile_idc == 118 ||
sps->profile_idc == 128 || sps->profile_idc == 138) {
radeon_bs_code_ue(&bs, 0x1); /* chroma_format_idc */
radeon_bs_code_ue(&bs, 0x0); /* bit_depth_luma_minus8 */
radeon_bs_code_ue(&bs, 0x0); /* bit_depth_chroma_minus8 */
radeon_bs_code_fixed_bits(&bs, 0x0, 2); /* qpprime_y_zero_transform_bypass_flag + seq_scaling_matrix_present_flag */
}
radeon_bs_code_ue(&bs, 3); /* log2_max_frame_num_minus4 */
radeon_bs_code_ue(&bs, sps->pic_order_cnt_type);
if (sps->pic_order_cnt_type == 0)
radeon_bs_code_ue(&bs, sps->log2_max_pic_order_cnt_lsb_minus4);
radeon_bs_code_ue(&bs, sps->max_num_ref_frames);
radeon_bs_code_fixed_bits(&bs, sps->gaps_in_frame_num_value_allowed_flag, 1);
radeon_bs_code_ue(&bs, DIV_ROUND_UP(enc->base.width, 16) - 1);
radeon_bs_code_ue(&bs, DIV_ROUND_UP(enc->base.height, 16) - 1);
radeon_bs_code_fixed_bits(&bs, 0x1, 1); /* frame_mbs_only_flag */
radeon_bs_code_fixed_bits(&bs, 0x1, 1); /* direct_8x8_inference_flag */
radeon_bs_code_fixed_bits(&bs, sps->enc_frame_cropping_flag, 1);
if (sps->enc_frame_cropping_flag) {
radeon_bs_code_ue(&bs, sps->enc_frame_crop_left_offset);
radeon_bs_code_ue(&bs, sps->enc_frame_crop_right_offset);
radeon_bs_code_ue(&bs, sps->enc_frame_crop_top_offset);
radeon_bs_code_ue(&bs, sps->enc_frame_crop_bottom_offset);
}
radeon_bs_code_fixed_bits(&bs, sps->vui_parameters_present_flag, 1);
if (sps->vui_parameters_present_flag) {
radeon_bs_code_fixed_bits(&bs, (sps->vui_flags.aspect_ratio_info_present_flag), 1);
if (sps->vui_flags.aspect_ratio_info_present_flag) {
radeon_bs_code_fixed_bits(&bs, (sps->aspect_ratio_idc), 8);
if (sps->aspect_ratio_idc == PIPE_H2645_EXTENDED_SAR) {
radeon_bs_code_fixed_bits(&bs, (sps->sar_width), 16);
radeon_bs_code_fixed_bits(&bs, (sps->sar_height), 16);
}
}
radeon_bs_code_fixed_bits(&bs, sps->vui_flags.overscan_info_present_flag, 1);
if (sps->vui_flags.overscan_info_present_flag)
radeon_bs_code_fixed_bits(&bs, sps->vui_flags.overscan_appropriate_flag, 1);
radeon_bs_code_fixed_bits(&bs, sps->vui_flags.video_signal_type_present_flag, 1);
if (sps->vui_flags.video_signal_type_present_flag) {
radeon_bs_code_fixed_bits(&bs, sps->video_format, 3);
radeon_bs_code_fixed_bits(&bs, sps->video_full_range_flag, 1);
radeon_bs_code_fixed_bits(&bs, sps->vui_flags.colour_description_present_flag, 1);
if (sps->vui_flags.colour_description_present_flag) {
radeon_bs_code_fixed_bits(&bs, sps->colour_primaries, 8);
radeon_bs_code_fixed_bits(&bs, sps->transfer_characteristics, 8);
radeon_bs_code_fixed_bits(&bs, sps->matrix_coefficients, 8);
}
}
radeon_bs_code_fixed_bits(&bs, sps->vui_flags.chroma_loc_info_present_flag, 1);
if (sps->vui_flags.chroma_loc_info_present_flag) {
radeon_bs_code_ue(&bs, sps->chroma_sample_loc_type_top_field);
radeon_bs_code_ue(&bs, sps->chroma_sample_loc_type_bottom_field);
}
radeon_bs_code_fixed_bits(&bs, (sps->vui_flags.timing_info_present_flag), 1);
if (sps->vui_flags.timing_info_present_flag) {
radeon_bs_code_fixed_bits(&bs, (sps->num_units_in_tick), 32);
radeon_bs_code_fixed_bits(&bs, (sps->time_scale), 32);
radeon_bs_code_fixed_bits(&bs, (sps->vui_flags.fixed_frame_rate_flag), 1);
}
radeon_bs_code_fixed_bits(&bs, sps->vui_flags.nal_hrd_parameters_present_flag, 1);
if (sps->vui_flags.nal_hrd_parameters_present_flag)
radeon_bs_h264_hrd_parameters(&bs, &sps->nal_hrd_parameters);
radeon_bs_code_fixed_bits(&bs, sps->vui_flags.vcl_hrd_parameters_present_flag, 1);
if (sps->vui_flags.vcl_hrd_parameters_present_flag)
radeon_bs_h264_hrd_parameters(&bs, &sps->vcl_hrd_parameters);
if (sps->vui_flags.nal_hrd_parameters_present_flag || sps->vui_flags.vcl_hrd_parameters_present_flag)
radeon_bs_code_fixed_bits(&bs, sps->vui_flags.low_delay_hrd_flag, 1);
radeon_bs_code_fixed_bits(&bs, sps->vui_flags.pic_struct_present_flag, 1);
radeon_bs_code_fixed_bits(&bs, sps->vui_flags.bitstream_restriction_flag, 1);
if (sps->vui_flags.bitstream_restriction_flag) {
radeon_bs_code_fixed_bits(&bs, 0x1, 1); /* motion_vectors_over_pic_boundaries_flag */
radeon_bs_code_ue(&bs, 0x2); /* max_bytes_per_pic_denom */
radeon_bs_code_ue(&bs, 0x1); /* max_bits_per_mb_denom */
radeon_bs_code_ue(&bs, 0x10); /* log2_max_mv_length_horizontal */
radeon_bs_code_ue(&bs, 0x10); /* log2_max_mv_length_vertical */
radeon_bs_code_ue(&bs, sps->max_num_reorder_frames);
radeon_bs_code_ue(&bs, sps->max_dec_frame_buffering);
}
}
radeon_bs_code_fixed_bits(&bs, 0x1, 1);
radeon_bs_byte_align(&bs);
radeon_bs_h264_sps(&bs, nal_byte, &sps);
return bs.bits_output / 8;
}
static unsigned int write_pps(struct rvce_encoder *enc, uint8_t nal_byte, uint8_t *out)
{
struct pipe_h264_enc_pic_control pps = enc->pic.pic_ctrl;
pps.deblocking_filter_control_present_flag = enc->enc_pic.pc.enc_loop_filter_disable ||
enc->enc_pic.pc.enc_lf_beta_offset || enc->enc_pic.pc.enc_lf_alpha_c0_offset;
pps.chroma_qp_index_offset = 0;
pps.transform_8x8_mode_flag = 0;
pps.second_chroma_qp_index_offset = 0;
struct radeon_bitstream bs;
radeon_bs_reset(&bs, out, NULL);
radeon_bs_set_emulation_prevention(&bs, false);
radeon_bs_code_fixed_bits(&bs, 0x00000001, 32);
radeon_bs_code_fixed_bits(&bs, nal_byte, 8);
radeon_bs_set_emulation_prevention(&bs, true);
radeon_bs_code_ue(&bs, 0x0); /* pic_parameter_set_id */
radeon_bs_code_ue(&bs, 0x0); /* seq_parameter_set_id */
radeon_bs_code_fixed_bits(&bs, enc->enc_pic.pc.enc_cabac_enable, 1);
radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* bottom_field_pic_order_in_frame_present_flag */
radeon_bs_code_ue(&bs, 0x0); /* num_slice_groups_minus_1 */
radeon_bs_code_ue(&bs, enc->enc_pic.pc.enc_num_default_active_ref_l0 - 1);
radeon_bs_code_ue(&bs, enc->enc_pic.pc.enc_num_default_active_ref_l1 - 1);
radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* weighted_pred_flag */
radeon_bs_code_fixed_bits(&bs, 0x0, 2); /* weighted_bipred_idc */
radeon_bs_code_se(&bs, 0x0); /* pic_init_qp_minus26 */
radeon_bs_code_se(&bs, 0x0); /* pic_init_qs_minus26 */
radeon_bs_code_se(&bs, 0x0); /* chroma_qp_index_offset */
bool deblocking_filter_present_flag =
enc->enc_pic.pc.enc_loop_filter_disable ||
enc->enc_pic.pc.enc_lf_beta_offset ||
enc->enc_pic.pc.enc_lf_alpha_c0_offset;
radeon_bs_code_fixed_bits(&bs, deblocking_filter_present_flag, 1);
radeon_bs_code_fixed_bits(&bs, enc->enc_pic.pc.enc_use_constrained_intra_pred, 1);
radeon_bs_code_fixed_bits(&bs, 0x0, 1); /* redundant_pic_cnt_present_flag */
radeon_bs_code_fixed_bits(&bs, 0x1, 1);
radeon_bs_byte_align(&bs);
radeon_bs_h264_pps(&bs, nal_byte, &pps);
return bs.bits_output / 8;
}