From 62715a6d039a7f2499ceca78476ebd42a5a03068 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 29 Nov 2022 08:59:23 +0100 Subject: [PATCH] radv: set missing SPI_SHADER_PGM_xxx registers on GFX11 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Found by inspection. Cc: 22.3 mesa-stable Signed-off-by: Samuel Pitoiset Reviewed-by: Timur Kristóf Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/si_cmd_buffer.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index f1e79249e6a..26bd2dd08d2 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -352,12 +352,15 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) if (physical_device->rad_info.gfx_level >= GFX10 && physical_device->rad_info.gfx_level < GFX11) { /* Logical CUs 16 - 31 */ - ac_set_reg_cu_en(cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS, S_00B404_CU_EN(0xffff), - C_00B404_CU_EN, 16, &physical_device->rad_info, - (void*)gfx10_set_sh_reg_idx3); ac_set_reg_cu_en(cs, R_00B104_SPI_SHADER_PGM_RSRC4_VS, S_00B104_CU_EN(0xffff), C_00B104_CU_EN, 16, &physical_device->rad_info, (void*)gfx10_set_sh_reg_idx3); + } + + if (physical_device->rad_info.gfx_level >= GFX10) { + ac_set_reg_cu_en(cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS, S_00B404_CU_EN(0xffff), + C_00B404_CU_EN, 16, &physical_device->rad_info, + (void*)gfx10_set_sh_reg_idx3); ac_set_reg_cu_en(cs, R_00B004_SPI_SHADER_PGM_RSRC4_PS, S_00B004_CU_EN(cu_mask_ps >> 16), C_00B004_CU_EN, 16, &physical_device->rad_info, (void*)gfx10_set_sh_reg_idx3);