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radeonsi: move index buffer flushing into a non-upload indexed case

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The other codepaths don't need this.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2017-02-15 18:36:21 +01:00
parent 22b8a773e1
commit 620aded541
1 changed files with 6 additions and 7 deletions
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13
src/gallium/drivers/radeonsi/si_state_draw.c
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@ -1086,16 +1086,15 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
return;
/* info->start will be added by the drawing code */
ib.offset -= start_offset;
} else if (sctx->b.chip_class <= CIK &&
r600_resource(ib.buffer)->TC_L2_dirty) {
/* VI reads index buffers through TC L2, so it doesn't
* need this. */
sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
r600_resource(ib.buffer)->TC_L2_dirty = false;
}
}
/* VI reads index buffers through TC L2. */
if (info->indexed && sctx->b.chip_class <= CIK &&
r600_resource(ib.buffer)->TC_L2_dirty) {
sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
r600_resource(ib.buffer)->TC_L2_dirty = false;
}
if (info->indirect) {
/* Add the buffer size for memory checking in need_cs_space. */
r600_context_add_resource_size(ctx, info->indirect);