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freedreno/a3xx: cache-flush is needed after MEM_WRITE
Otherwise the mem2gmem blit would see potentially bogus texture coordinates. Fixes an issue that shows up with glamor. CC: "11.0" <mesa-stable@lists.freedesktop.org> Signed-off-by: Rob Clark <robclark@freedesktop.org>
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3 changed files with 14 additions and 5 deletions
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@ -798,11 +798,7 @@ fd3_emit_restore(struct fd_context *ctx)
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OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
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A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
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OUT_PKT0(ring, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG, 2);
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OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0));
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OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) |
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A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(INVALIDATE) |
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A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE);
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fd3_emit_cache_flush(ctx, ring);
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OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
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OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
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@ -90,4 +90,15 @@ void fd3_emit_restore(struct fd_context *ctx);
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void fd3_emit_init(struct pipe_context *pctx);
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static inline void
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fd3_emit_cache_flush(struct fd_context *ctx, struct fd_ringbuffer *ring)
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{
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fd_wfi(ctx, ring);
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OUT_PKT0(ring, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG, 2);
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OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0));
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OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) |
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A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(INVALIDATE) |
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A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE);
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}
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#endif /* FD3_EMIT_H */
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@ -558,6 +558,8 @@ fd3_emit_tile_mem2gmem(struct fd_context *ctx, struct fd_tile *tile)
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OUT_RING(ring, fui(x1));
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OUT_RING(ring, fui(y1));
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fd3_emit_cache_flush(ctx, ring);
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for (i = 0; i < 4; i++) {
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OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
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OUT_RING(ring, A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
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