fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-04-21 22:50:37 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 3

radv: only need to force emit the TCS regs on Vega10 and Raven1

Browse source 
Other GFX9 chips aren't affected.

Cc: "19.0" "19.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset 2019-05-02 17:44:39 +02:00
parent b3a26d4628
commit 62001f3dff
1 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/amd/vulkan/radv_nir_to_llvm.c
View file

@ -3690,8 +3690,8 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
if (shader_count >= 2)
ac_init_exec_full_mask(&ctx.ac);
if (ctx.ac.chip_class == GFX9 &&
ctx.ac.family != CHIP_VEGA20 &&
if ((ctx.ac.family == CHIP_VEGA10 ||
ctx.ac.family == CHIP_RAVEN) &&
shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
ac_nir_fixup_ls_hs_input_vgprs(&ctx);