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https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-01-11 08:00:13 +01:00
zink: remove gfx program slot mapping
if shaders aren't being shared between programs, they can instead directly assign io between the shader stages such that only the producer and consumer pair need to have their slots match up this requires that each gfx program struct stores base nir for a given shader in order to avoid breaking io for other programs which reuse shader states Reviewed-by: Dave Airlie <airlied@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11691>
This commit is contained in:
Mike Blumenkrantz
Marge Bot
parent
a8448a91e6
commit
61f2667cf5
4 changed files with 170 additions and 138 deletions
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@ -524,69 +524,155 @@ update_so_info(struct zink_shader *zs, const struct pipe_stream_output_info *so_
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}
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static void
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assign_io_locations(nir_shader *nir, unsigned char *shader_slot_map,
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unsigned char *shader_slots_reserved)
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assign_producer_var_io(gl_shader_stage stage, nir_variable *var, unsigned *reserved, unsigned char *slot_map)
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{
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unsigned reserved = shader_slots_reserved ? *shader_slots_reserved : 0;
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nir_foreach_variable_with_modes(var, nir, nir_var_shader_in | nir_var_shader_out) {
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if ((nir->info.stage == MESA_SHADER_VERTEX && var->data.mode == nir_var_shader_in) ||
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(nir->info.stage == MESA_SHADER_FRAGMENT && var->data.mode == nir_var_shader_out))
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continue;
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unsigned slot = var->data.location;
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switch (var->data.location) {
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case VARYING_SLOT_POS:
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case VARYING_SLOT_PNTC:
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case VARYING_SLOT_PSIZ:
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case VARYING_SLOT_LAYER:
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case VARYING_SLOT_PRIMITIVE_ID:
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case VARYING_SLOT_CLIP_DIST0:
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case VARYING_SLOT_CULL_DIST0:
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case VARYING_SLOT_VIEWPORT:
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case VARYING_SLOT_FACE:
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case VARYING_SLOT_TESS_LEVEL_OUTER:
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case VARYING_SLOT_TESS_LEVEL_INNER:
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/* use a sentinel value to avoid counting later */
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var->data.driver_location = UINT_MAX;
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break;
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unsigned slot = var->data.location;
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switch (var->data.location) {
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case VARYING_SLOT_POS:
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case VARYING_SLOT_PNTC:
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case VARYING_SLOT_PSIZ:
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case VARYING_SLOT_LAYER:
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case VARYING_SLOT_PRIMITIVE_ID:
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case VARYING_SLOT_CLIP_DIST0:
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case VARYING_SLOT_CULL_DIST0:
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case VARYING_SLOT_VIEWPORT:
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case VARYING_SLOT_FACE:
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case VARYING_SLOT_TESS_LEVEL_OUTER:
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case VARYING_SLOT_TESS_LEVEL_INNER:
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/* use a sentinel value to avoid counting later */
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var->data.driver_location = UINT_MAX;
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break;
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default:
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if (var->data.patch) {
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assert(var->data.location >= VARYING_SLOT_PATCH0);
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slot = var->data.location - VARYING_SLOT_PATCH0;
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} else if (var->data.location >= VARYING_SLOT_VAR0 &&
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((var->data.mode == nir_var_shader_out &&
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nir->info.stage == MESA_SHADER_TESS_CTRL) ||
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(var->data.mode != nir_var_shader_out &&
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nir->info.stage == MESA_SHADER_TESS_EVAL))) {
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slot = var->data.location - VARYING_SLOT_VAR0;
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} else {
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if (shader_slot_map[var->data.location] == 0xff) {
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assert(reserved < MAX_VARYING);
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shader_slot_map[var->data.location] = reserved;
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if (nir->info.stage == MESA_SHADER_TESS_CTRL && var->data.location >= VARYING_SLOT_VAR0)
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reserved += (glsl_count_vec4_slots(var->type, false, false) / 32 /*MAX_PATCH_VERTICES*/);
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else
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reserved += glsl_count_vec4_slots(var->type, false, false);
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}
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slot = shader_slot_map[var->data.location];
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assert(slot < MAX_VARYING);
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default:
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if (var->data.patch) {
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assert(var->data.location >= VARYING_SLOT_PATCH0);
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slot = var->data.location - VARYING_SLOT_PATCH0;
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} else if (var->data.location >= VARYING_SLOT_VAR0 &&
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var->data.mode == nir_var_shader_in &&
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stage == MESA_SHADER_TESS_EVAL) {
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slot = var->data.location - VARYING_SLOT_VAR0;
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} else {
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if (slot_map[var->data.location] == 0xff) {
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assert(*reserved < MAX_VARYING);
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slot_map[var->data.location] = *reserved;
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*reserved += glsl_count_vec4_slots(var->type, false, false);
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}
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var->data.driver_location = slot;
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slot = slot_map[var->data.location];
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assert(slot < MAX_VARYING);
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}
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var->data.driver_location = slot;
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}
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}
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ALWAYS_INLINE static bool
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is_texcoord(gl_shader_stage stage, const nir_variable *var)
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{
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if (stage != MESA_SHADER_FRAGMENT)
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return false;
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return var->data.location >= VARYING_SLOT_TEX0 &&
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var->data.location <= VARYING_SLOT_TEX7;
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}
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static bool
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assign_consumer_var_io(gl_shader_stage stage, nir_variable *var, unsigned *reserved, unsigned char *slot_map)
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{
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switch (var->data.location) {
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case VARYING_SLOT_POS:
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case VARYING_SLOT_PNTC:
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case VARYING_SLOT_PSIZ:
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case VARYING_SLOT_LAYER:
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case VARYING_SLOT_PRIMITIVE_ID:
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case VARYING_SLOT_CLIP_DIST0:
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case VARYING_SLOT_CULL_DIST0:
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case VARYING_SLOT_VIEWPORT:
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case VARYING_SLOT_FACE:
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case VARYING_SLOT_TESS_LEVEL_OUTER:
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case VARYING_SLOT_TESS_LEVEL_INNER:
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/* use a sentinel value to avoid counting later */
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var->data.driver_location = UINT_MAX;
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break;
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default:
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if (var->data.patch) {
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assert(var->data.location >= VARYING_SLOT_PATCH0);
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var->data.driver_location = var->data.location - VARYING_SLOT_PATCH0;
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} else if (var->data.location >= VARYING_SLOT_VAR0 &&
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stage == MESA_SHADER_TESS_CTRL &&
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var->data.mode == nir_var_shader_out)
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var->data.driver_location = var->data.location - VARYING_SLOT_VAR0;
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else {
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if (slot_map[var->data.location] == (unsigned char)-1) {
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if (!is_texcoord(stage, var))
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/* dead io */
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return false;
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/* texcoords can't be eliminated in fs due to GL_COORD_REPLACE */
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slot_map[var->data.location] = (*reserved)++;
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}
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var->data.driver_location = slot_map[var->data.location];
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}
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}
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return true;
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}
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if (shader_slots_reserved)
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*shader_slots_reserved = reserved;
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static bool
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rewrite_and_discard_read(nir_builder *b, nir_instr *instr, void *data)
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{
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nir_variable *var = data;
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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if (intr->intrinsic != nir_intrinsic_load_deref)
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return false;
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nir_variable *deref_var = nir_intrinsic_get_var(intr, 0);
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if (deref_var != var)
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return false;
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nir_ssa_def *undef = nir_ssa_undef(b, nir_dest_num_components(intr->dest), nir_dest_bit_size(intr->dest));
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nir_ssa_def_rewrite_uses(&intr->dest.ssa, undef);
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return true;
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}
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void
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zink_compiler_assign_io(nir_shader *producer, nir_shader *consumer)
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{
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unsigned reserved = 0;
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unsigned char slot_map[VARYING_SLOT_MAX];
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memset(slot_map, -1, sizeof(slot_map));
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bool do_fixup = false;
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nir_shader *nir = producer->info.stage == MESA_SHADER_TESS_CTRL ? producer : consumer;
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if (producer->info.stage == MESA_SHADER_TESS_CTRL) {
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/* never assign from tcs -> tes, always invert */
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nir_foreach_variable_with_modes(var, consumer, nir_var_shader_in)
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assign_producer_var_io(consumer->info.stage, var, &reserved, slot_map);
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nir_foreach_variable_with_modes_safe(var, producer, nir_var_shader_out) {
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if (!assign_consumer_var_io(producer->info.stage, var, &reserved, slot_map))
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/* this is an output, nothing more needs to be done for it to be dropped */
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do_fixup = true;
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}
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} else {
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nir_foreach_variable_with_modes(var, producer, nir_var_shader_out)
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assign_producer_var_io(producer->info.stage, var, &reserved, slot_map);
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nir_foreach_variable_with_modes_safe(var, consumer, nir_var_shader_in) {
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if (!assign_consumer_var_io(consumer->info.stage, var, &reserved, slot_map)) {
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do_fixup = true;
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/* input needs to be rewritten as an undef to ensure the entire deref chain is deleted */
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nir_shader_instructions_pass(consumer, rewrite_and_discard_read, nir_metadata_dominance, var);
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}
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}
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}
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if (!do_fixup)
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return;
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nir_fixup_deref_modes(nir);
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NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_shader_temp, NULL);
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optimize_nir(nir);
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}
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VkShaderModule
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zink_shader_compile(struct zink_screen *screen, struct zink_shader *zs, struct zink_shader_key *key,
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unsigned char *shader_slot_map, unsigned char *shader_slots_reserved)
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zink_shader_compile(struct zink_screen *screen, struct zink_shader *zs, nir_shader *base_nir, struct zink_shader_key *key)
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{
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VkShaderModule mod = VK_NULL_HANDLE;
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void *streamout = NULL;
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nir_shader *nir = nir_shader_clone(NULL, zs->nir);
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nir_shader *nir = nir_shader_clone(NULL, base_nir);
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if (key) {
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if (key->inline_uniforms) {
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@ -640,8 +726,6 @@ zink_shader_compile(struct zink_screen *screen, struct zink_shader *zs, struct z
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}
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NIR_PASS_V(nir, nir_convert_from_ssa, true);
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assign_io_locations(nir, shader_slot_map, shader_slots_reserved);
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struct spirv_shader *spirv = nir_to_spirv(nir, streamout, screen->spirv_version);
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if (!spirv)
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goto done;
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@ -93,10 +93,10 @@ struct zink_shader {
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void
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zink_screen_init_compiler(struct zink_screen *screen);
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void
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zink_compiler_assign_io(nir_shader *producer, nir_shader *consumer);
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VkShaderModule
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zink_shader_compile(struct zink_screen *screen, struct zink_shader *zs, struct zink_shader_key *key,
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unsigned char *shader_slot_map, unsigned char *shader_slots_reserved);
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zink_shader_compile(struct zink_screen *screen, struct zink_shader *zs, nir_shader *nir, struct zink_shader_key *key);
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struct zink_shader *
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zink_shader_create(struct zink_screen *screen, struct nir_shader *nir,
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@ -249,8 +249,7 @@ get_shader_module_for_stage(struct zink_context *ctx, struct zink_shader *zs, st
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return NULL;
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}
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pipe_reference_init(&zm->reference, 1);
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mod = zink_shader_compile(zink_screen(ctx->base.screen), zs, &key,
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prog->shader_slot_map, &prog->shader_slots_reserved);
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mod = zink_shader_compile(zink_screen(ctx->base.screen), zs, prog->nir[stage], &key);
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if (!mod) {
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ralloc_free(keybox);
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FREE(zm);
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@ -370,82 +369,6 @@ equals_gfx_pipeline_state(const void *a, const void *b)
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!memcmp(a, b, offsetof(struct zink_gfx_pipeline_state, hash));
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}
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static void
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init_slot_map(struct zink_context *ctx, struct zink_gfx_program *prog)
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{
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unsigned existing_shaders = 0;
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bool needs_new_map = false;
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/* if there's a case where we'll be reusing any shaders, we need to (maybe) reuse the slot map too */
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if (ctx->curr_program) {
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for (int i = 0; i < ZINK_SHADER_COUNT; ++i) {
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if (ctx->curr_program->shaders[i])
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existing_shaders |= 1 << i;
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}
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/* if there's reserved slots, check whether we have enough remaining slots */
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if (ctx->curr_program->shader_slots_reserved) {
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uint64_t max_outputs = 0;
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uint32_t num_xfb_outputs = 0;
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for (int i = 0; i < ZINK_SHADER_COUNT; ++i) {
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if (i != PIPE_SHADER_TESS_CTRL &&
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i != PIPE_SHADER_FRAGMENT &&
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ctx->gfx_stages[i]) {
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uint32_t user_outputs = ctx->gfx_stages[i]->nir->info.outputs_written >> 32;
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uint32_t builtin_outputs = ctx->gfx_stages[i]->nir->info.outputs_written;
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num_xfb_outputs = MAX2(num_xfb_outputs, ctx->gfx_stages[i]->streamout.so_info.num_outputs);
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unsigned user_outputs_count = 0;
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/* check builtins first */
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u_foreach_bit(slot, builtin_outputs) {
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switch (slot) {
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/* none of these require slot map entries */
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case VARYING_SLOT_POS:
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case VARYING_SLOT_PSIZ:
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case VARYING_SLOT_LAYER:
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case VARYING_SLOT_PRIMITIVE_ID:
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case VARYING_SLOT_CULL_DIST0:
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case VARYING_SLOT_CLIP_DIST0:
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case VARYING_SLOT_VIEWPORT:
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case VARYING_SLOT_TESS_LEVEL_INNER:
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case VARYING_SLOT_TESS_LEVEL_OUTER:
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break;
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default:
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/* remaining legacy builtins only require 1 slot each */
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if (ctx->curr_program->shader_slot_map[slot] == -1)
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user_outputs_count++;
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break;
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}
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}
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u_foreach_bit(slot, user_outputs) {
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if (ctx->curr_program->shader_slot_map[slot] == -1) {
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/* user variables can span multiple slots */
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nir_variable *var = nir_find_variable_with_location(ctx->gfx_stages[i]->nir,
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nir_var_shader_out, slot);
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assert(var);
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if (i == PIPE_SHADER_TESS_CTRL && var->data.location >= VARYING_SLOT_VAR0)
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user_outputs_count += (glsl_count_vec4_slots(var->type, false, false) / 32 /*MAX_PATCH_VERTICES*/);
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else
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user_outputs_count += glsl_count_vec4_slots(var->type, false, false);
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}
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}
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max_outputs = MAX2(max_outputs, user_outputs_count);
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}
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}
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/* slot map can only hold 32 entries, so dump this one if we'll exceed that */
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if (ctx->curr_program->shader_slots_reserved + max_outputs + num_xfb_outputs > 32)
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needs_new_map = true;
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}
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}
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if (needs_new_map || ctx->dirty_shader_stages == existing_shaders || !existing_shaders) {
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/* all shaders are being recompiled: new slot map */
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memset(prog->shader_slot_map, -1, sizeof(prog->shader_slot_map));
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} else {
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/* at least some shaders are being reused: use existing slot map so locations match up */
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memcpy(prog->shader_slot_map, ctx->curr_program->shader_slot_map, sizeof(prog->shader_slot_map));
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prog->shader_slots_reserved = ctx->curr_program->shader_slots_reserved;
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}
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}
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void
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zink_update_gfx_program(struct zink_context *ctx, struct zink_gfx_program *prog)
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{
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@ -489,6 +412,32 @@ zink_pipeline_layout_create(struct zink_screen *screen, struct zink_program *pg)
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return layout;
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}
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static void
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assign_io(struct zink_gfx_program *prog, struct zink_shader *stages[ZINK_SHADER_COUNT])
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{
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struct zink_shader *shaders[PIPE_SHADER_TYPES];
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/* build array in pipeline order */
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for (unsigned i = 0; i < ZINK_SHADER_COUNT; i++)
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shaders[tgsi_processor_to_shader_stage(i)] = stages[i];
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for (unsigned i = 0; i < MESA_SHADER_FRAGMENT;) {
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nir_shader *producer = shaders[i]->nir;
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for (unsigned j = i + 1; j < ZINK_SHADER_COUNT; i++, j++) {
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struct zink_shader *consumer = shaders[j];
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if (!consumer)
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continue;
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if (!prog->nir[producer->info.stage])
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prog->nir[producer->info.stage] = nir_shader_clone(prog, producer);
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if (!prog->nir[j])
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prog->nir[j] = nir_shader_clone(prog, consumer->nir);
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zink_compiler_assign_io(prog->nir[producer->info.stage], prog->nir[j]);
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i = j;
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break;
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}
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}
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}
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struct zink_gfx_program *
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zink_create_gfx_program(struct zink_context *ctx,
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struct zink_shader *stages[ZINK_SHADER_COUNT])
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@ -513,7 +462,7 @@ zink_create_gfx_program(struct zink_context *ctx,
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ctx->dirty_shader_stages |= BITFIELD_BIT(PIPE_SHADER_TESS_CTRL);
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}
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init_slot_map(ctx, prog);
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assign_io(prog, prog->shaders);
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update_shader_modules(ctx, prog->shaders, prog, false);
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@ -604,7 +553,7 @@ zink_create_compute_program(struct zink_context *ctx, struct zink_shader *shader
|
|||
comp->module = CALLOC_STRUCT(zink_shader_module);
|
||||
assert(comp->module);
|
||||
pipe_reference_init(&comp->module->reference, 1);
|
||||
comp->module->shader = zink_shader_compile(screen, shader, NULL, NULL, NULL);
|
||||
comp->module->shader = zink_shader_compile(screen, shader, shader->nir, NULL);
|
||||
assert(comp->module->shader);
|
||||
_mesa_hash_table_insert(&comp->base.shader_cache[0], &shader->shader_id, comp->module);
|
||||
|
||||
|
|
|
|||
|
|
@ -90,13 +90,12 @@ struct zink_program {
|
|||
struct zink_gfx_program {
|
||||
struct zink_program base;
|
||||
|
||||
struct nir_shader *nir[ZINK_SHADER_COUNT];
|
||||
struct zink_shader_module *modules[ZINK_SHADER_COUNT]; // compute stage doesn't belong here
|
||||
|
||||
struct zink_shader_module *default_variants[ZINK_SHADER_COUNT][2]; //[default, no streamout]
|
||||
const void *default_variant_key[ZINK_SHADER_COUNT];
|
||||
struct zink_shader *shaders[ZINK_SHADER_COUNT];
|
||||
unsigned char shader_slot_map[VARYING_SLOT_MAX];
|
||||
unsigned char shader_slots_reserved;
|
||||
struct hash_table *pipelines[11]; // number of draw modes we support
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue