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etnaviv: Switch to stream_count from etna_core_info
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30806>
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4 changed files with 4 additions and 7 deletions
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@ -335,7 +335,7 @@ etna_emit_state(struct etna_context *ctx)
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for (int x = 0; x < ctx->vertex_buffer.count; ++x) {
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/*14600*/ EMIT_STATE_RELOC(NFE_VERTEX_STREAMS_BASE_ADDR(x), &ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR);
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}
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} else if(screen->specs.stream_count > 1) { /* hw w/ multiple vertex streams */
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} else if(screen->info->gpu.stream_count > 1) { /* hw w/ multiple vertex streams */
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for (int x = 0; x < ctx->vertex_buffer.count; ++x) {
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/*00680*/ EMIT_STATE_RELOC(FE_VERTEX_STREAMS_BASE_ADDR(x), &ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR);
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}
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@ -349,7 +349,7 @@ etna_emit_state(struct etna_context *ctx)
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if (ctx->vertex_buffer.cvb[x].FE_VERTEX_STREAM_BASE_ADDR.bo) {
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if (screen->info->halti >= 2)
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/*14640*/ EMIT_STATE(NFE_VERTEX_STREAMS_CONTROL(x), ctx->vertex_elements->FE_VERTEX_STREAM_CONTROL[x]);
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else if (screen->specs.stream_count > 1)
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else if (screen->info->gpu.stream_count > 1)
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/*006A0*/ EMIT_STATE(FE_VERTEX_STREAMS_CONTROL(x), ctx->vertex_elements->FE_VERTEX_STREAM_CONTROL[x]);
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else
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/*00650*/ EMIT_STATE(FE_VERTEX_STREAM_CONTROL, ctx->vertex_elements->FE_VERTEX_STREAM_CONTROL[0]);
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@ -103,8 +103,6 @@ struct etna_specs {
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unsigned vertex_sampler_count;
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/* maximum number of vertex element configurations */
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unsigned vertex_max_elements;
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/* number of vertex streams */
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unsigned stream_count;
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/* vertex shader memory address*/
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uint32_t vs_offset;
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/* pixel shader memory address*/
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@ -216,7 +216,7 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
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return 255;
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case PIPE_CAP_MAX_VERTEX_BUFFERS:
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return screen->specs.stream_count;
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return screen->info->gpu.stream_count;
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case PIPE_CAP_VS_INSTANCEID:
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case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
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return VIV_FEATURE(screen, ETNA_FEATURE_HALTI2);
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@ -852,7 +852,6 @@ etna_get_specs(struct etna_screen *screen)
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/* Copy all relevant limits from etna_core_info. */
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if (info->type == ETNA_CORE_GPU) {
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instruction_count = info->gpu.max_instructions;
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screen->specs.stream_count = info->gpu.stream_count;
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screen->specs.pixel_pipes = info->gpu.pixel_pipes;
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screen->specs.max_varyings = MIN2(info->gpu.max_varyings, ETNA_NUM_VARYINGS);
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@ -562,7 +562,7 @@ etna_vertex_elements_state_create(struct pipe_context *pctx,
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start_offset = elements[idx].src_offset;
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/* guaranteed by PIPE_CAP_MAX_VERTEX_BUFFERS */
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assert(buffer_idx < screen->specs.stream_count);
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assert(buffer_idx < screen->info->gpu.stream_count);
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/* maximum vertex size is 256 bytes */
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assert(element_size != 0 && (end_offset - start_offset) < 256);
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