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amd: lower load_subgroup_invocation in NIR

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Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32782>
This commit is contained in:
Marek Olšák 2024-12-25 12:44:59 -05:00 • committed by Marge Bot
parent e69f47faee
commit 61bfb4fa06
5 changed files with 5 additions and 10 deletions
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3
src/amd/common/ac_nir.c
View file

@ -401,6 +401,9 @@ lower_intrinsic_to_arg(nir_builder *b, nir_instr *instr, void *state)
nir_imul_imm(b, load_subgroup_id_lowered(s, b), s->wave_size));
}
break;
case nir_intrinsic_load_subgroup_invocation:
replacement = nir_mbcnt_amd(b, nir_imm_intN_t(b, ~0ull, s->wave_size), nir_imm_int(b, 0));
break;
default:
return false;
}

4
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -8139,10 +8139,6 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr)
break;
}
case nir_intrinsic_load_subgroup_invocation: {
emit_mbcnt(ctx, get_ssa_temp(ctx, &instr->def));
break;
}
case nir_intrinsic_ballot_relaxed:
case nir_intrinsic_ballot: {
Temp src = get_ssa_temp(ctx, instr->src[0].ssa);

1
src/amd/compiler/aco_instruction_selection_setup.cpp
View file

@ -550,7 +550,6 @@ init_context(isel_context* ctx, nir_shader* shader)
case nir_intrinsic_load_per_vertex_input:
case nir_intrinsic_load_per_vertex_output:
case nir_intrinsic_load_interpolated_input:
case nir_intrinsic_load_subgroup_invocation:
case nir_intrinsic_load_tess_coord:
case nir_intrinsic_write_invocation_amd:
case nir_intrinsic_mbcnt_amd:

4
src/amd/compiler/tests/test_isel.cpp
View file

@ -1671,9 +1671,9 @@ BEGIN_TEST(isel.cf.empty_exec.repair_ssa)
//>> BB6
//! /* logical preds: BB5, / linear preds: BB5, / kind: uniform, */
//>> s1: %sgpr0 = p_parallelcopy 42
//>> v1: %vgpr0 = v_mbcnt_hi_u32_b32_e64 -1, %_
//>> v1: %vgpr0 = v_mbcnt_hi_u32_b32_e64 %_, %_
val_sgpr = nir_imm_int(nb, 42);
val_vgpr = nir_load_subgroup_invocation(nb);
val_vgpr = nir_mbcnt_amd(nb, nir_imm_intN_t(nb, UINT64_MAX, 64), nir_imm_int(nb, 0));
//>> BB7
//! /* logical preds: BB6, / linear preds: BB6, / kind: uniform, break, */

3
src/amd/llvm/ac_nir_to_llvm.c
View file

@ -2774,9 +2774,6 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins
case nir_intrinsic_as_uniform:
result = ac_build_readlane(&ctx->ac, get_src(ctx, instr->src[0]), NULL);
break;
case nir_intrinsic_load_subgroup_invocation:
result = ac_get_thread_id(&ctx->ac);
break;
case nir_intrinsic_load_workgroup_id: {
LLVMValueRef values[3] = {ctx->ac.i32_0, ctx->ac.i32_0, ctx->ac.i32_0};