diff --git a/src/gallium/drivers/radeonsi/gfx/si_gfx.h b/src/gallium/drivers/radeonsi/gfx/si_gfx.h
index be95bbb83ef..6141f21e856 100644
--- a/src/gallium/drivers/radeonsi/gfx/si_gfx.h
+++ b/src/gallium/drivers/radeonsi/gfx/si_gfx.h
@@ -7,6 +7,7 @@
 #ifndef SI_GFX_H
 #define SI_GFX_H
 
+#include "si_pipe.h"
 #include "util/mesa-blake3.h"
 #include "util/u_stub_gfx_compute.h"
 #include "ac_sqtt.h"
@@ -121,6 +122,45 @@ void si_init_task_mesh_shader_functions(struct si_context *sctx);
 void si_nir_lower_mediump_io_default(struct nir_shader *nir);
 void si_nir_lower_mediump_io_option(struct nir_shader *nir);
 
+static inline void si_need_gfx_cs_space(struct si_context *ctx, unsigned num_draws,
+                                        unsigned extra_dw_per_draw)
+{
+   struct radeon_cmdbuf *cs = &ctx->gfx_cs;
+   /* Don't count the needed CS space exactly and just use an upper bound.
+    *
+    * Also reserve space for stopping queries at the end of IB, because
+    * the number of active queries is unlimited in theory.
+    */
+   unsigned reserve_dw = 2048 + ctx->num_cs_dw_queries_suspend +
+      num_draws * (10 + extra_dw_per_draw);
+
+   if (!ctx->ws->cs_check_space(cs, reserve_dw))
+      si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
+}
+
+static inline void si_select_draw_vbo(struct si_context *sctx)
+{
+   pipe_draw_func draw_vbo = sctx->draw_vbo[!!sctx->shader.tes.cso]
+                                           [!!sctx->shader.gs.cso]
+                                           [sctx->ngg];
+   pipe_draw_vertex_state_func draw_vertex_state =
+      sctx->draw_vertex_state[!!sctx->shader.tes.cso]
+                             [!!sctx->shader.gs.cso]
+                             [sctx->ngg];
+   assert(draw_vbo);
+   assert(draw_vertex_state);
+
+   if (unlikely(sctx->real_draw_vbo)) {
+      assert(sctx->real_draw_vertex_state);
+      sctx->real_draw_vbo = draw_vbo;
+      sctx->real_draw_vertex_state = draw_vertex_state;
+   } else {
+      assert(!sctx->real_draw_vertex_state);
+      sctx->b.draw_vbo = draw_vbo;
+      sctx->b.draw_vertex_state = draw_vertex_state;
+   }
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
index b2808d13e9e..7c7ac698e72 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -5,6 +5,7 @@
  */
 
 #include "si_pipe.h"
+#include "gfx/si_gfx.h"
 #include "sid.h"
 #include "si_build_pm4.h"
 #include "ac_cmdbuf_cp.h"
diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c b/src/gallium/drivers/radeonsi/si_perfcounter.c
index 4cc658bfa2e..77f5b07ea19 100644
--- a/src/gallium/drivers/radeonsi/si_perfcounter.c
+++ b/src/gallium/drivers/radeonsi/si_perfcounter.c
@@ -6,6 +6,7 @@
 
 #include "si_build_pm4.h"
 #include "si_query.h"
+#include "gfx/si_gfx.h"
 #include "util/u_memory.h"
 
 #include "ac_cmdbuf_cp.h"
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 097f18afb02..2c17b229fc4 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -1981,22 +1981,6 @@ static inline bool util_rast_prim_is_triangles(unsigned prim)
    return ((1 << prim) & UTIL_ALL_PRIM_TRIANGLE_MODES) != 0;
 }
 
-static inline void si_need_gfx_cs_space(struct si_context *ctx, unsigned num_draws,
-                                        unsigned extra_dw_per_draw)
-{
-   struct radeon_cmdbuf *cs = &ctx->gfx_cs;
-   /* Don't count the needed CS space exactly and just use an upper bound.
-    *
-    * Also reserve space for stopping queries at the end of IB, because
-    * the number of active queries is unlimited in theory.
-    */
-   unsigned reserve_dw = 2048 + ctx->num_cs_dw_queries_suspend +
-      num_draws * (10 + extra_dw_per_draw);
-
-   if (!ctx->ws->cs_check_space(cs, reserve_dw))
-      si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
-}
-
 /**
  * Add a buffer to the buffer list for the given command stream (CS).
  *
@@ -2015,29 +1999,6 @@ static inline void radeon_add_to_buffer_list(struct si_context *sctx, struct rad
                            bo->domains);
 }
 
-static inline void si_select_draw_vbo(struct si_context *sctx)
-{
-   pipe_draw_func draw_vbo = sctx->draw_vbo[!!sctx->shader.tes.cso]
-                                           [!!sctx->shader.gs.cso]
-                                           [sctx->ngg];
-   pipe_draw_vertex_state_func draw_vertex_state =
-      sctx->draw_vertex_state[!!sctx->shader.tes.cso]
-                             [!!sctx->shader.gs.cso]
-                             [sctx->ngg];
-   assert(draw_vbo);
-   assert(draw_vertex_state);
-
-   if (unlikely(sctx->real_draw_vbo)) {
-      assert(sctx->real_draw_vertex_state);
-      sctx->real_draw_vbo = draw_vbo;
-      sctx->real_draw_vertex_state = draw_vertex_state;
-   } else {
-      assert(!sctx->real_draw_vertex_state);
-      sctx->b.draw_vbo = draw_vbo;
-      sctx->b.draw_vertex_state = draw_vertex_state;
-   }
-}
-
 /* Return the number of samples that the rasterizer uses. */
 static inline unsigned si_get_num_coverage_samples(struct si_context *sctx)
 {
diff --git a/src/gallium/drivers/radeonsi/si_query.c b/src/gallium/drivers/radeonsi/si_query.c
index 428ff5c1a8d..61f1ba7e1d6 100644
--- a/src/gallium/drivers/radeonsi/si_query.c
+++ b/src/gallium/drivers/radeonsi/si_query.c
@@ -7,6 +7,7 @@
  */
 
 #include "si_query.h"
+#include "gfx/si_gfx.h"
 #include "si_build_pm4.h"
 
 #include "amd/common/sid.h"