From 61a845ca19f7c1d236a7f517108c6ddb3b929c64 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 17 May 2021 10:17:52 -0400 Subject: [PATCH] ac/surface: don't set DCC_PIPE_ALIGN modifier bit for gfx10 with 1 RB Acked-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/amd/common/ac_surface.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index c20f9eb24cb..ac130807766 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -300,7 +300,6 @@ bool ac_get_supported_modifiers(const struct radeon_info *info, if (info->max_render_backends == 1) { ADD_MOD(AMD_FMT_MOD | common_dcc | - AMD_FMT_MOD_SET(DCC_PIPE_ALIGN, 1) | AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, independent_128b) | AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B))