diff --git a/src/freedreno/ir3/ir3_ra.c b/src/freedreno/ir3/ir3_ra.c index 39d34bb51d9..ff273de1b08 100644 --- a/src/freedreno/ir3/ir3_ra.c +++ b/src/freedreno/ir3/ir3_ra.c @@ -702,6 +702,15 @@ ra_block_compute_live_ranges(struct ir3_ra_ctx *ctx, struct ir3_block *block) block->data = bd; + struct ir3_instruction *first_non_input = NULL; + list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) { + if (instr->opc != OPC_META_INPUT) { + first_non_input = instr; + break; + } + } + + list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) { struct ir3_instruction *src; struct ir3_register *reg; @@ -771,6 +780,9 @@ ra_block_compute_live_ranges(struct ir3_ra_ctx *ctx, struct ir3_block *block) def(name, id->defn); + if (instr->opc == OPC_META_INPUT) + use(name, first_non_input); + if (is_high(id->defn)) { ra_set_node_class(ctx->g, name, ctx->set->high_classes[id->cls - HIGH_OFFSET]); diff --git a/src/freedreno/ir3/ir3_sched.c b/src/freedreno/ir3/ir3_sched.c index 34c648a6748..c828b5da6c1 100644 --- a/src/freedreno/ir3/ir3_sched.c +++ b/src/freedreno/ir3/ir3_sched.c @@ -783,18 +783,28 @@ sched_block(struct ir3_sched_ctx *ctx, struct ir3_block *block) list_inithead(&block->instr_list); list_inithead(&ctx->depth_list); - /* first a pre-pass to schedule all meta:input instructions - * (which need to appear first so that RA knows the register is - * occupied), and move remaining to depth sorted list: + /* First schedule all meta:input instructions, followed by + * tex-prefetch. We want all of the instructions that load + * values into registers before the shader starts to go + * before any other instructions. But in particular we + * want inputs to come before prefetches. This is because + * a FS's bary_ij input may not actually be live in the + * shader, but it should not be scheduled on top of any + * other input (but can be overwritten by a tex prefetch) + * + * Finally, move all the remaining instructions to the depth- + * list */ - list_for_each_entry_safe (struct ir3_instruction, instr, &unscheduled_list, node) { - if ((instr->opc == OPC_META_INPUT) || - (instr->opc == OPC_META_TEX_PREFETCH)) { + list_for_each_entry_safe (struct ir3_instruction, instr, &unscheduled_list, node) + if (instr->opc == OPC_META_INPUT) schedule(ctx, instr); - } else { - ir3_insert_by_depth(instr, &ctx->depth_list); - } - } + + list_for_each_entry_safe (struct ir3_instruction, instr, &unscheduled_list, node) + if (instr->opc == OPC_META_TEX_PREFETCH) + schedule(ctx, instr); + + list_for_each_entry_safe (struct ir3_instruction, instr, &unscheduled_list, node) + ir3_insert_by_depth(instr, &ctx->depth_list); while (!list_is_empty(&ctx->depth_list)) { struct ir3_sched_notes notes = {0};