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freedreno/registers: Update with GS, HS and DS registers
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
This commit is contained in:
Kristian H. Kristensen
parent
628ed1bbd5
commit
610c8c938e
6 changed files with 108 additions and 12 deletions
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@ -1825,9 +1825,18 @@ to upconvert to 32b float internally?
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<reg32 offset="0x8000" name="GRAS_UNKNOWN_8000"/>
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<reg32 offset="0x8001" name="GRAS_UNKNOWN_8001"/>
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<reg32 offset="0x8003" name="GRAS_UNKNOWN_8003"/>
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<!-- always 0x0 ? -->
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<reg32 offset="0x8004" name="GRAS_UNKNOWN_8004"/>
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<enum name="a6xx_layer_type">
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<value value="0x0" name="MULTISAMPLE_ARRAY"/>
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<value value="0x1" name="ARRAY"/> <!-- 2d array and 3d -->
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<value value="0x2" name="CUBEMAP"/>
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</enum>
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<reg32 offset="0x8004" name="GRAS_LAYER_CNTL">
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<bitfield name="LAYERED" pos="0" type="boolean"/>
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<bitfield name="TYPE" low="1" high="2" type="a6xx_layer_type"/>
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</reg32>
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<reg32 offset="0x8005" name="GRAS_CNTL">
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<!-- see also RB_RENDER_CONTROL0 -->
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@ -1891,6 +1900,10 @@ to upconvert to 32b float internally?
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<!-- always 0x0 ? -->
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<reg32 offset="0x809b" name="GRAS_UNKNOWN_809B"/>
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<reg32 offset="0x809c" name="GRAS_UNKNOWN_809C">
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<bitfield name="GS_WRITES_LAYER" pos="0" type="boolean"/>
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</reg32>
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<reg32 offset="0x80a0" name="GRAS_UNKNOWN_80A0"/>
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<reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL">
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@ -1961,8 +1974,9 @@ to upconvert to 32b float internally?
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</enum>
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<bitset name="a6xx_2d_blit_cntl" inline="yes">
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<bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/>
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<bitfield name="SOLID_COLOR" low="7" high="7" type="boolean"/>
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<bitfield name="ROTATE" low="0" high="1" type="a6xx_rotation"/>
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<bitfield name="HORIZONTAL_FLIP" low="2" high="2" type="boolean"/>
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<bitfield name="SOLID_COLOR" pos="7" type="boolean"/>
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<bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_color_fmt"/>
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<bitfield name="SCISSOR" pos="16" type="boolean"/>
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<!-- required when blitting D24S8/D24X8 -->
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@ -2367,11 +2381,18 @@ to upconvert to 32b float internally?
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<reg32 offset="0x8e07" name="RB_CCU_CNTL"/> <!-- always 7c400004 or 10000000 -->
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<reg32 offset="0x9100" name="VPC_UNKNOWN_9100"/>
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<!-- always 0x00ffff00 ? */ -->
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<reg32 offset="0x9101" name="VPC_UNKNOWN_9101"/>
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<reg32 offset="0x9101" name="VPC_UNKNOWN_9102"/>
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<reg32 offset="0x9104" name="VPC_GS_SIV_CNTL"/>
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<reg32 offset="0x9105" name="VPC_UNKNOWN_9105">
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<bitfield name="LAYERLOC" low="0" high="7" type="uint"/>
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</reg32>
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<reg32 offset="0x9107" name="VPC_UNKNOWN_9107"/>
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<reg32 offset="0x9108" name="VPC_UNKNOWN_9108"/>
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@ -2441,6 +2462,22 @@ to upconvert to 32b float internally?
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<bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
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</reg32>
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<reg32 offset="0x9302" name="VPC_PACK_GS">
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<doc>
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num of varyings plus four for gl_Position (plus one if gl_PointSize)
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plus # of transform-feedback (streamout) varyings if using the
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hw streamout (rather than stg instructions in shader)
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</doc>
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<bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
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<bitfield name="POSITIONLOC" low="8" high="15" type="uint"/>
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<!--
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This seems to be the OUTLOC for the psize output. It could possibly
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be the max-OUTLOC position, but it is only set when VS writes psize
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(and blob always puts psize at highest OUTLOC)
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-->
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<bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
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</reg32>
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<reg32 offset="0x9303" name="VPC_PACK_3">
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<doc>
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domain shader version of VPC_PACK
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@ -2529,6 +2566,16 @@ to upconvert to 32b float internally?
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<bitfield name="PSIZE" pos="8" type="boolean"/>
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</reg32>
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<reg32 offset="0x9b02" name="PC_PRIMITIVE_CNTL_2">
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<doc>
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geometry shader
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</doc>
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<bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
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<bitfield name="PSIZE" pos="8" type="boolean"/>
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<bitfield name="LAYER" pos="9" type="boolean"/>
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<bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/>
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</reg32>
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<reg32 offset="0x9b03" name="PC_PRIMITIVE_CNTL_3">
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<doc>
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hull shader?
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@ -2551,8 +2598,22 @@ to upconvert to 32b float internally?
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<bitfield name="PSIZE" pos="8" type="boolean"/>
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</reg32>
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<!-- always 0x0 ? -->
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<reg32 offset="0x9b06" name="PC_UNKNOWN_9B06"/>
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<reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5">
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<doc>
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geometry shader
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</doc>
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<bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/>
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<bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/>
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<bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/>
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</reg32>
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<reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6">
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<doc>
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size in vec4s of per-primitive storage for gs
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</doc>
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<bitfield name="STRIDE_IN_VPC" low="0" high="8" type="uint"/>
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</reg32>
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<reg32 offset="0x9b07" name="PC_UNKNOWN_9B07"/>
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<reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR_LO"/>
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@ -2581,6 +2642,7 @@ to upconvert to 32b float internally?
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<reg32 offset="0xa004" name="VFD_CONTROL_4">
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</reg32>
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<reg32 offset="0xa005" name="VFD_CONTROL_5">
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<bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/>
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</reg32>
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<reg32 offset="0xa006" name="VFD_CONTROL_6">
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</reg32>
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@ -2737,6 +2799,31 @@ to upconvert to 32b float internally?
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<reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
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<reg32 offset="0xa871" name="SP_GS_UNKNOWN_A871"/>
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<reg32 offset="0xa873" name="SP_PRIMITIVE_CNTL_GS">
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<!-- # of VS outputs including pos/psize -->
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<bitfield name="GSOUT" low="0" high="4" type="uint"/>
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<bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/>
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</reg32>
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<array offset="0xa874" name="SP_GS_OUT" stride="1" length="16">
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<reg32 offset="0x0" name="REG">
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<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
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<bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
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<bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
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<bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
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</reg32>
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</array>
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<array offset="0xa884" name="SP_GS_VPC_DST" stride="1" length="8">
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<reg32 offset="0x0" name="REG">
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<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
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<bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
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<bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
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<bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
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</reg32>
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</array>
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<reg32 offset="0xa88d" name="SP_GS_OBJ_START_LO"/>
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<reg32 offset="0xa88e" name="SP_GS_OBJ_START_HI"/>
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<reg32 offset="0xa893" name="SP_GS_TEX_COUNT" type="uint"/>
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@ -2761,6 +2848,14 @@ to upconvert to 32b float internally?
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<reg32 offset="0xa8af" name="SP_GS_TEX_CONST_HI"/>
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<reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
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<reg32 offset="0xa981" name="SP_UNKNOWN_A981">
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<bitfield name="FACE0" pos="0" type="boolean"/>
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<bitfield name="FACE1" pos="1" type="boolean"/>
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<bitfield name="FACE2" pos="2" type="boolean"/>
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<bitfield name="FACE3" pos="3" type="boolean"/>
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<bitfield name="FACE4" pos="4" type="boolean"/>
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<bitfield name="FACE5" pos="5" type="boolean"/>
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</reg32>
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<reg32 offset="0xa982" name="SP_UNKNOWN_A982"/>
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<reg32 offset="0xa983" name="SP_FS_OBJ_START_LO"/>
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<reg32 offset="0xa984" name="SP_FS_OBJ_START_HI"/>
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@ -643,6 +643,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
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<bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/>
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<bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/>
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<bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/>
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<bitfield name="GS_ENABLE" pos="16" type="boolean"/>
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<bitfield name="TESS_ENABLE" pos="17" type="boolean"/>
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</bitset>
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@ -953,8 +953,8 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
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tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9806, 0);
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tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
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tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B06, 0);
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tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B06, 0);
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tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
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tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9B07, 0);
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tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0);
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@ -1141,7 +1141,7 @@ tu6_emit_gras_unknowns(struct tu_cs *cs)
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tu_cs_emit(cs, 0x80);
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tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8001, 1);
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tu_cs_emit(cs, 0x0);
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tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8004, 1);
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tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LAYER_CNTL, 1);
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tu_cs_emit(cs, 0x0);
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}
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@ -1261,8 +1261,8 @@ t7 opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
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WRITE(REG_A6XX_PC_UNKNOWN_9806, 0);
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WRITE(REG_A6XX_PC_UNKNOWN_9980, 0);
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WRITE(REG_A6XX_PC_UNKNOWN_9B06, 0);
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WRITE(REG_A6XX_PC_UNKNOWN_9B06, 0);
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WRITE(REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);
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WRITE(REG_A6XX_PC_UNKNOWN_9B07, 0);
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WRITE(REG_A6XX_SP_UNKNOWN_A81B, 0);
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@ -111,7 +111,7 @@ fd6_rasterizer_state_create(struct pipe_context *pctx,
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OUT_RING(ring, 0x80);
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OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8001, 1);
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OUT_RING(ring, 0x0);
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OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8004, 1);
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OUT_PKT4(ring, REG_A6XX_GRAS_LAYER_CNTL, 1);
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OUT_RING(ring, 0x0);
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OUT_PKT4(ring, REG_A6XX_GRAS_SU_CNTL, 1);
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