From 610a19cf3112d2122a2bb6c1883c068373ac1cdd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20Sch=C3=BCrmann?= Date: Mon, 30 Jun 2025 09:33:19 +0200 Subject: [PATCH] aco/isel: allow to select SGPR defs for vectorized bcsel and logical operations No fossil changes. Part-of: --- src/amd/compiler/instruction_selection/aco_isel_setup.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/amd/compiler/instruction_selection/aco_isel_setup.cpp b/src/amd/compiler/instruction_selection/aco_isel_setup.cpp index b3623f92a15..c3b8ca081c2 100644 --- a/src/amd/compiler/instruction_selection/aco_isel_setup.cpp +++ b/src/amd/compiler/instruction_selection/aco_isel_setup.cpp @@ -5,6 +5,7 @@ */ #include "aco_instruction_selection.h" +#include "aco_interface.h" #include "nir_builder.h" #include "nir_control_flow.h" @@ -398,9 +399,9 @@ init_context(isel_context* ctx, nir_shader* shader) nir_alu_instr* alu_instr = nir_instr_as_alu(instr); RegType type = RegType::sgpr; - /* packed 16bit instructions have to be VGPR */ + /* Packed 16-bit instructions have to be VGPR. */ if (alu_instr->def.num_components == 2 && - nir_op_infos[alu_instr->op].output_size == 0) + aco_nir_op_supports_packed_math_16bit(alu_instr)) type = RegType::vgpr; switch (alu_instr->op) {