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r300: rename state

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According to r300_reg.h from radeon drm module 0x4f30 is ZB_ZMASK_OFFSET.
Also cleanup as trailing whitespaces.
This commit is contained in:
Maciej Cencora 2009-04-19 21:25:01 +02:00 • committed by Dave Airlie
parent 931c89f6f6
commit 607c6cf188
4 changed files with 15 additions and 9 deletions
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12
src/mesa/drivers/dri/r300/r300_cmdbuf.c
View file

@ -83,7 +83,7 @@ void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
BATCH_LOCALS(&r300->radeon);
drm_r300_cmd_header_t cmd;
uint32_t addr, ndw, i;
if (!r300->radeon.radeonScreen->kernel_mm) {
uint32_t dwords;
dwords = (*atom->check) (ctx, atom);
@ -92,7 +92,7 @@ void emit_vpu(GLcontext *ctx, struct radeon_state_atom * atom)
END_BATCH();
return;
}
cmd.u = atom->cmd[0];
addr = (cmd.vpu.adrhi << 8) | cmd.vpu.adrlo;
ndw = cmd.vpu.count * 4;
@ -175,7 +175,7 @@ static void emit_tex_offsets(GLcontext *ctx, struct radeon_state_atom * atom)
for(i = 0; i < numtmus; ++i) {
radeonTexObj *t = r300->hw.textures[i];
if (!t)
notexture = 1;
}
@ -304,7 +304,7 @@ static void emit_zb_offset(GLcontext *ctx, struct radeon_state_atom * atom)
if (rrb->bo->flags & RADEON_BO_FLAGS_MICRO_TILE){
zbpitch |= R300_DEPTHMICROTILE_TILED;
}
BEGIN_BATCH_NO_AUTOSTATE(6);
OUT_BATCH_REGSEQ(R300_ZB_DEPTHOFFSET, 1);
OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
@ -606,8 +606,8 @@ void r300InitCmdBuf(r300ContextPtr r300)
r300->hw.zb.emit = emit_zb_offset;
ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_DEPTHCLEARVALUE, 1);
ALLOC_STATE(unk4F30, always, 3, 0);
r300->hw.unk4F30.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, 0x4F30, 2);
ALLOC_STATE(zb_zmask, always, 3, 0);
r300->hw.zb_zmask.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_ZMASK_OFFSET, 2);
ALLOC_STATE(zb_hiz_offset, always, 2, 0);
r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(r300->radeon.radeonScreen, R300_ZB_HIZ_OFFSET, 1);
ALLOC_STATE(zb_hiz_pitch, always, 2, 0);

2
src/mesa/drivers/dri/r300/r300_context.h
View file

@ -351,7 +351,7 @@ struct r300_hw_state {
struct radeon_state_atom zstencil_format;
struct radeon_state_atom zb; /* z buffer (4F20) */
struct radeon_state_atom zb_depthclearvalue; /* (4F28) */
struct radeon_state_atom unk4F30; /* (4F30) */
struct radeon_state_atom zb_zmask; /* (4F30) */
struct radeon_state_atom zb_hiz_offset; /* (4F44) */
struct radeon_state_atom zb_hiz_pitch; /* (4F54) */

6
src/mesa/drivers/dri/r300/r300_reg.h
View file

@ -2432,6 +2432,12 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
/* Z Buffer Clear Value */
#define R300_ZB_DEPTHCLEARVALUE 0x4f28
#define R300_ZB_ZMASK_OFFSET 0x4f30
#define R300_ZB_ZMASK_PITCH 0x4f34
#define R300_ZB_ZMASK_WRINDEX 0x4f38
#define R300_ZB_ZMASK_DWORD 0x4f3c
#define R300_ZB_ZMASK_RDINDEX 0x4f40
/* Hierarchical Z Memory Offset */
#define R300_ZB_HIZ_OFFSET 0x4f44

4
src/mesa/drivers/dri/r300/r300_state.c
View file

@ -2205,8 +2205,8 @@ static void r300ResetHwState(r300ContextPtr r300)
r300->hw.zstencil_format.cmd[4] = 0x00000000;
r300SetEarlyZState(ctx);
r300->hw.unk4F30.cmd[1] = 0;
r300->hw.unk4F30.cmd[2] = 0;
r300->hw.zb_zmask.cmd[1] = 0;
r300->hw.zb_zmask.cmd[2] = 0;
r300->hw.zb_hiz_offset.cmd[1] = 0;