diff --git a/src/nouveau/compiler/nak/assign_regs.rs b/src/nouveau/compiler/nak/assign_regs.rs
index 75b2b1781f6..51c90b27baa 100644
--- a/src/nouveau/compiler/nak/assign_regs.rs
+++ b/src/nouveau/compiler/nak/assign_regs.rs
@@ -716,7 +716,7 @@ fn instr_remap_srcs_file(instr: &mut Instr, ra: &mut VecRegAllocator) {
     // scalar sources.
     for src in instr.srcs_mut() {
         if let Some(ssa) = src_ssa_ref(src) {
-            if ssa.file().unwrap() == ra.file() && ssa.comps() > 1 {
+            if ssa.file() == ra.file() && ssa.comps() > 1 {
                 let reg = ra.collect_vector(ssa);
                 src_set_reg(src, reg);
             }
@@ -731,7 +731,7 @@ fn instr_remap_srcs_file(instr: &mut Instr, ra: &mut VecRegAllocator) {
 
     for src in instr.srcs_mut() {
         if let Some(ssa) = src_ssa_ref(src) {
-            if ssa.file().unwrap() == ra.file() && ssa.comps() == 1 {
+            if ssa.file() == ra.file() && ssa.comps() == 1 {
                 let reg = ra.collect_vector(ssa);
                 src_set_reg(src, reg);
             }
@@ -748,7 +748,7 @@ fn instr_alloc_scalar_dsts_file(
 ) {
     for dst in instr.dsts_mut() {
         if let Dst::SSA(ssa) = dst {
-            if ssa.file().unwrap() == ra.file() {
+            if ssa.file() == ra.file() {
                 assert!(ssa.comps() == 1);
                 let reg = ra.alloc_scalar(ip, sum, phi_webs, ssa[0]);
                 *dst = RegRef::new(ra.file(), reg, 1).into();
@@ -777,7 +777,7 @@ fn instr_assign_regs_file(
     let mut vec_dst_comps = 0;
     for (i, dst) in instr.dsts().iter().enumerate() {
         if let Dst::SSA(ssa) = dst {
-            if ssa.file().unwrap() == ra.file() && ssa.comps() > 1 {
+            if ssa.file() == ra.file() && ssa.comps() > 1 {
                 vec_dsts.push(VecDst {
                     dst_idx: i,
                     comps: ssa.comps(),
@@ -899,7 +899,7 @@ fn instr_assign_regs_file(
         // Scalar destinations can fill in holes.
         for dst in instr.dsts_mut() {
             if let Dst::SSA(ssa) = dst {
-                if ssa.file().unwrap() == vra.file() && ssa.comps() > 1 {
+                if ssa.file() == vra.file() && ssa.comps() > 1 {
                     *dst = vra.alloc_vector(ssa).into();
                 }
             }
@@ -1102,7 +1102,7 @@ impl AssignRegsBlock {
                     // support vectors because cbuf handles are vec2s. However,
                     // since we only have a single scalar destination, we can
                     // just allocate and free killed up-front.
-                    let ra = &mut self.ra[ssa.file().unwrap()];
+                    let ra = &mut self.ra[ssa.file()];
                     let mut vra = VecRegAllocator::new(ra);
                     let reg = vra.collect_vector(ssa);
                     vra.free_killed(srcs_killed);
@@ -1145,7 +1145,7 @@ impl AssignRegsBlock {
                 if srcs_killed.len() == src_vec.comps().into()
                     && src_vec.file() == dst_vec.file()
                 {
-                    let ra = &mut self.ra[src_vec.file().unwrap()];
+                    let ra = &mut self.ra[src_vec.file()];
                     let mut vra = VecRegAllocator::new(ra);
                     let reg = vra.collect_vector(src_vec);
                     vra.finish(pcopy);
@@ -1168,7 +1168,7 @@ impl AssignRegsBlock {
                     // case.
                     assert!(dst_vec.comps() > 1 || srcs_killed.is_empty());
 
-                    let dst_ra = &mut self.ra[dst_vec.file().unwrap()];
+                    let dst_ra = &mut self.ra[dst_vec.file()];
                     let mut vra = VecRegAllocator::new(dst_ra);
                     let dst_reg = vra.alloc_vector(dst_vec);
                     vra.finish(pcopy);
diff --git a/src/nouveau/compiler/nak/builder.rs b/src/nouveau/compiler/nak/builder.rs
index bc0b374d247..7abfb222014 100644
--- a/src/nouveau/compiler/nak/builder.rs
+++ b/src/nouveau/compiler/nak/builder.rs
@@ -865,7 +865,7 @@ pub trait SSABuilder: Builder {
     }
 
     fn bmov_to_bar(&mut self, src: Src) -> SSAValue {
-        assert!(src.src_ref.as_ssa().unwrap().file() == Some(RegFile::GPR));
+        assert!(src.src_ref.as_ssa().unwrap().file() == RegFile::GPR);
         let dst = self.alloc_ssa(RegFile::Bar);
         self.push_op(OpBMov {
             dst: dst.into(),
@@ -876,7 +876,7 @@ pub trait SSABuilder: Builder {
     }
 
     fn bmov_to_gpr(&mut self, src: Src) -> SSAValue {
-        assert!(src.src_ref.as_ssa().unwrap().file() == Some(RegFile::Bar));
+        assert!(src.src_ref.as_ssa().unwrap().file() == RegFile::Bar);
         let dst = self.alloc_ssa(RegFile::GPR);
         self.push_op(OpBMov {
             dst: dst.into(),
diff --git a/src/nouveau/compiler/nak/ir.rs b/src/nouveau/compiler/nak/ir.rs
index ff26ef47856..c91c1de80af 100644
--- a/src/nouveau/compiler/nak/ir.rs
+++ b/src/nouveau/compiler/nak/ir.rs
@@ -601,7 +601,7 @@ impl SrcRef {
 
     pub fn is_carry(&self) -> bool {
         match self {
-            SrcRef::SSA(ssa) => ssa.file() == Some(RegFile::Carry),
+            SrcRef::SSA(ssa) => ssa.file() == RegFile::Carry,
             SrcRef::Reg(reg) => reg.file() == RegFile::Carry,
             _ => false,
         }
@@ -610,7 +610,7 @@ impl SrcRef {
     #[allow(dead_code)]
     pub fn is_barrier(&self) -> bool {
         match self {
-            SrcRef::SSA(ssa) => ssa.file() == Some(RegFile::Bar),
+            SrcRef::SSA(ssa) => ssa.file() == RegFile::Bar,
             SrcRef::Reg(reg) => reg.file() == RegFile::Bar,
             _ => false,
         }
@@ -1107,7 +1107,7 @@ impl Src {
 
     pub fn is_upred_reg(&self) -> bool {
         match &self.src_ref {
-            SrcRef::SSA(ssa) => ssa.file() == Some(RegFile::UPred),
+            SrcRef::SSA(ssa) => ssa.file() == RegFile::UPred,
             SrcRef::Reg(reg) => reg.file() == RegFile::UPred,
             _ => false,
         }
@@ -1302,7 +1302,7 @@ fn all_dsts_uniform(dsts: &[Dst]) -> bool {
         let dst_uniform = match dst {
             Dst::None => continue,
             Dst::Reg(r) => r.is_uniform(),
-            Dst::SSA(r) => r.file().unwrap().is_uniform(),
+            Dst::SSA(r) => r.file().is_uniform(),
         };
         assert!(uniform.is_none() || uniform == Some(dst_uniform));
         uniform = Some(dst_uniform);
diff --git a/src/nouveau/compiler/nak/legalize.rs b/src/nouveau/compiler/nak/legalize.rs
index 81a8b2bc4eb..b9216f0d6fb 100644
--- a/src/nouveau/compiler/nak/legalize.rs
+++ b/src/nouveau/compiler/nak/legalize.rs
@@ -28,7 +28,7 @@ pub fn src_is_upred_reg(src: &Src) -> bool {
 pub fn src_is_reg(src: &Src, reg_file: RegFile) -> bool {
     match &src.src_ref {
         SrcRef::Zero | SrcRef::True | SrcRef::False => true,
-        SrcRef::SSA(ssa) => ssa.file() == Some(reg_file),
+        SrcRef::SSA(ssa) => ssa.file() == reg_file,
         SrcRef::Imm32(_) | SrcRef::CBuf(_) => false,
         SrcRef::Reg(_) => panic!("Not in SSA form"),
     }
@@ -446,7 +446,7 @@ fn legalize_instr(
                         && vec.comps() > 1
                         && !pinned.contains(vec)
                     {
-                        b.copy_ssa_ref(vec, vec.file().unwrap().to_warp());
+                        b.copy_ssa_ref(vec, vec.file().to_warp());
                     }
                 }
                 SrcRef::CBuf(CBufRef {
diff --git a/src/nouveau/compiler/nak/sm120_instr_latencies.rs b/src/nouveau/compiler/nak/sm120_instr_latencies.rs
index c3e20e324a7..bf31edf70c9 100644
--- a/src/nouveau/compiler/nak/sm120_instr_latencies.rs
+++ b/src/nouveau/compiler/nak/sm120_instr_latencies.rs
@@ -411,7 +411,7 @@ impl SM120Latency {
     ) -> u32 {
         let dst_file = match &write.dsts_as_slice()[dst_idx] {
             Dst::None => return 0,
-            Dst::SSA(vec) => vec.file().unwrap(),
+            Dst::SSA(vec) => vec.file(),
             Dst::Reg(reg) => reg.file(),
         };
 
@@ -468,7 +468,7 @@ impl SM120Latency {
     pub fn war(read: &Op, src_idx: usize, write: &Op, dst_idx: usize) -> u32 {
         let dst_file = match &write.dsts_as_slice()[dst_idx] {
             Dst::None => return 0,
-            Dst::SSA(vec) => vec.file().unwrap(),
+            Dst::SSA(vec) => vec.file(),
             Dst::Reg(reg) => reg.file(),
         };
 
@@ -513,7 +513,7 @@ impl SM120Latency {
     ) -> u32 {
         let dst_file = match &a.dsts_as_slice()[a_dst_idx] {
             Dst::None => return 0,
-            Dst::SSA(vec) => vec.file().unwrap(),
+            Dst::SSA(vec) => vec.file(),
             Dst::Reg(reg) => reg.file(),
         };
 
diff --git a/src/nouveau/compiler/nak/sm50.rs b/src/nouveau/compiler/nak/sm50.rs
index 5c18dfd3082..78136a02149 100644
--- a/src/nouveau/compiler/nak/sm50.rs
+++ b/src/nouveau/compiler/nak/sm50.rs
@@ -13,7 +13,7 @@ use std::ops::Range;
 pub fn instr_latency(_sm: u8, op: &Op, dst_idx: usize) -> u32 {
     let file = match &op.dsts_as_slice()[dst_idx] {
         Dst::None => return 0,
-        Dst::SSA(vec) => vec.file().unwrap(),
+        Dst::SSA(vec) => vec.file(),
         Dst::Reg(reg) => reg.file(),
     };
 
diff --git a/src/nouveau/compiler/nak/sm70.rs b/src/nouveau/compiler/nak/sm70.rs
index 165735222fa..e03b116ef1a 100644
--- a/src/nouveau/compiler/nak/sm70.rs
+++ b/src/nouveau/compiler/nak/sm70.rs
@@ -24,7 +24,7 @@ impl ShaderModel70 {
     fn instr_latency(&self, op: &Op, dst_idx: usize) -> u32 {
         let file = match &op.dsts_as_slice()[dst_idx] {
             Dst::None => return 0,
-            Dst::SSA(vec) => vec.file().unwrap(),
+            Dst::SSA(vec) => vec.file(),
             Dst::Reg(reg) => reg.file(),
         };
 
diff --git a/src/nouveau/compiler/nak/sm70_encode.rs b/src/nouveau/compiler/nak/sm70_encode.rs
index b3af4f491e8..48107515261 100644
--- a/src/nouveau/compiler/nak/sm70_encode.rs
+++ b/src/nouveau/compiler/nak/sm70_encode.rs
@@ -310,7 +310,7 @@ fn src_mod_is_bnot(src_mod: SrcMod) -> bool {
 fn dst_is_bar(dst: &Dst) -> bool {
     match dst {
         Dst::None => false,
-        Dst::SSA(ssa) => ssa.file().unwrap() == RegFile::Bar,
+        Dst::SSA(ssa) => ssa.file() == RegFile::Bar,
         Dst::Reg(reg) => reg.file() == RegFile::Bar,
     }
 }
diff --git a/src/nouveau/compiler/nak/sm75_instr_latencies.rs b/src/nouveau/compiler/nak/sm75_instr_latencies.rs
index bccf4ac5995..a052d75007e 100644
--- a/src/nouveau/compiler/nak/sm75_instr_latencies.rs
+++ b/src/nouveau/compiler/nak/sm75_instr_latencies.rs
@@ -1216,7 +1216,7 @@ impl SM75Latency {
     ) -> u32 {
         let dst_file = match &write.dsts_as_slice()[dst_idx] {
             Dst::None => return 0,
-            Dst::SSA(vec) => vec.file().unwrap(),
+            Dst::SSA(vec) => vec.file(),
             Dst::Reg(reg) => reg.file(),
         };
 
@@ -1275,7 +1275,7 @@ impl SM75Latency {
     pub fn war(read: &Op, src_idx: usize, write: &Op, dst_idx: usize) -> u32 {
         let dst_file = match &write.dsts_as_slice()[dst_idx] {
             Dst::None => return 0,
-            Dst::SSA(vec) => vec.file().unwrap(),
+            Dst::SSA(vec) => vec.file(),
             Dst::Reg(reg) => reg.file(),
         };
 
@@ -1331,7 +1331,7 @@ impl SM75Latency {
     ) -> u32 {
         let dst_file = match &a.dsts_as_slice()[a_dst_idx] {
             Dst::None => return 0,
-            Dst::SSA(vec) => vec.file().unwrap(),
+            Dst::SSA(vec) => vec.file(),
             Dst::Reg(reg) => reg.file(),
         };
 
diff --git a/src/nouveau/compiler/nak/sm80_instr_latencies.rs b/src/nouveau/compiler/nak/sm80_instr_latencies.rs
index be91a617f43..860f1f4fb62 100644
--- a/src/nouveau/compiler/nak/sm80_instr_latencies.rs
+++ b/src/nouveau/compiler/nak/sm80_instr_latencies.rs
@@ -1437,7 +1437,7 @@ impl SM80Latency {
     ) -> u32 {
         let dst_file = match &write.dsts_as_slice()[dst_idx] {
             Dst::None => return 0,
-            Dst::SSA(vec) => vec.file().unwrap(),
+            Dst::SSA(vec) => vec.file(),
             Dst::Reg(reg) => reg.file(),
         };
 
@@ -1494,7 +1494,7 @@ impl SM80Latency {
     pub fn war(read: &Op, src_idx: usize, write: &Op, dst_idx: usize) -> u32 {
         let dst_file = match &write.dsts_as_slice()[dst_idx] {
             Dst::None => return 0,
-            Dst::SSA(vec) => vec.file().unwrap(),
+            Dst::SSA(vec) => vec.file(),
             Dst::Reg(reg) => reg.file(),
         };
 
@@ -1546,7 +1546,7 @@ impl SM80Latency {
     ) -> u32 {
         let dst_file = match &a.dsts_as_slice()[a_dst_idx] {
             Dst::None => return 0,
-            Dst::SSA(vec) => vec.file().unwrap(),
+            Dst::SSA(vec) => vec.file(),
             Dst::Reg(reg) => reg.file(),
         };
 
diff --git a/src/nouveau/compiler/nak/spill_values.rs b/src/nouveau/compiler/nak/spill_values.rs
index d55eb76034d..f63ce5e706f 100644
--- a/src/nouveau/compiler/nak/spill_values.rs
+++ b/src/nouveau/compiler/nak/spill_values.rs
@@ -232,7 +232,7 @@ impl Spill for SpillGPR<'_> {
         assert!(dst.file() == RegFile::Mem);
         self.info.num_spills_to_mem += 1;
         if let Some(ssa) = src.as_ssa() {
-            assert!(ssa.file() == Some(RegFile::GPR));
+            assert!(ssa.file() == RegFile::GPR);
             Instr::new_boxed(OpCopy {
                 dst: dst.into(),
                 src: src,
diff --git a/src/nouveau/compiler/nak/ssa_value.rs b/src/nouveau/compiler/nak/ssa_value.rs
index 3b551487bea..cc9c7c664f2 100644
--- a/src/nouveau/compiler/nak/ssa_value.rs
+++ b/src/nouveau/compiler/nak/ssa_value.rs
@@ -204,17 +204,17 @@ impl SSARef {
         }
     }
 
-    /// Returns the register file for this SSA reference, if all SSA values have
-    /// the same register file.
-    pub fn file(&self) -> Option<RegFile> {
+    /// Returns the register file for this SSA reference, assuming all SSA
+    /// values have the same register file.
+    pub fn file(&self) -> RegFile {
         let comps = usize::from(self.comps());
         let file = self[0].file();
         for i in 1..comps {
             if self[i].file() != file {
-                return None;
+                panic!("SSARef mixes RegFiles")
             }
         }
-        Some(file)
+        file
     }
 
     /// Returns true if this SSA reference is known to be uniform.