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i965: Create a shared enum for hardware and compiler-internal opcodes.

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This should make gdbing more pleasant, and it might be used in sharing
part of the codegen between the VS and FS backends.
This commit is contained in:
Eric Anholt 2011-05-03 10:55:50 -07:00
parent c1f00731fd
commit 6034b9a512
7 changed files with 120 additions and 126 deletions
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134
src/mesa/drivers/dri/i965/brw_defines.h
View file

@ -557,58 +557,88 @@
#define BRW_WE_ALL 1
/** @} */
#define BRW_OPCODE_MOV 1
#define BRW_OPCODE_SEL 2
#define BRW_OPCODE_NOT 4
#define BRW_OPCODE_AND 5
#define BRW_OPCODE_OR 6
#define BRW_OPCODE_XOR 7
#define BRW_OPCODE_SHR 8
#define BRW_OPCODE_SHL 9
#define BRW_OPCODE_RSR 10
#define BRW_OPCODE_RSL 11
#define BRW_OPCODE_ASR 12
#define BRW_OPCODE_CMP 16
#define BRW_OPCODE_CMPN 17
#define BRW_OPCODE_JMPI 32
#define BRW_OPCODE_IF 34
#define BRW_OPCODE_IFF 35
#define BRW_OPCODE_ELSE 36
#define BRW_OPCODE_ENDIF 37
#define BRW_OPCODE_DO 38
#define BRW_OPCODE_WHILE 39
#define BRW_OPCODE_BREAK 40
#define BRW_OPCODE_CONTINUE 41
#define BRW_OPCODE_HALT 42
#define BRW_OPCODE_MSAVE 44
#define BRW_OPCODE_MRESTORE 45
#define BRW_OPCODE_PUSH 46
#define BRW_OPCODE_POP 47
#define BRW_OPCODE_WAIT 48
#define BRW_OPCODE_SEND 49
#define BRW_OPCODE_SENDC 50
#define BRW_OPCODE_MATH 56
#define BRW_OPCODE_ADD 64
#define BRW_OPCODE_MUL 65
#define BRW_OPCODE_AVG 66
#define BRW_OPCODE_FRC 67
#define BRW_OPCODE_RNDU 68
#define BRW_OPCODE_RNDD 69
#define BRW_OPCODE_RNDE 70
#define BRW_OPCODE_RNDZ 71
#define BRW_OPCODE_MAC 72
#define BRW_OPCODE_MACH 73
#define BRW_OPCODE_LZD 74
#define BRW_OPCODE_SAD2 80
#define BRW_OPCODE_SADA2 81
#define BRW_OPCODE_DP4 84
#define BRW_OPCODE_DPH 85
#define BRW_OPCODE_DP3 86
#define BRW_OPCODE_DP2 87
#define BRW_OPCODE_DPA2 88
#define BRW_OPCODE_LINE 89
#define BRW_OPCODE_PLN 90
#define BRW_OPCODE_NOP 126
enum opcode {
/* These are the actual hardware opcodes. */
BRW_OPCODE_MOV = 1,
BRW_OPCODE_SEL = 2,
BRW_OPCODE_NOT = 4,
BRW_OPCODE_AND = 5,
BRW_OPCODE_OR = 6,
BRW_OPCODE_XOR = 7,
BRW_OPCODE_SHR = 8,
BRW_OPCODE_SHL = 9,
BRW_OPCODE_RSR = 10,
BRW_OPCODE_RSL = 11,
BRW_OPCODE_ASR = 12,
BRW_OPCODE_CMP = 16,
BRW_OPCODE_CMPN = 17,
BRW_OPCODE_JMPI = 32,
BRW_OPCODE_IF = 34,
BRW_OPCODE_IFF = 35,
BRW_OPCODE_ELSE = 36,
BRW_OPCODE_ENDIF = 37,
BRW_OPCODE_DO = 38,
BRW_OPCODE_WHILE = 39,
BRW_OPCODE_BREAK = 40,
BRW_OPCODE_CONTINUE = 41,
BRW_OPCODE_HALT = 42,
BRW_OPCODE_MSAVE = 44,
BRW_OPCODE_MRESTORE = 45,
BRW_OPCODE_PUSH = 46,
BRW_OPCODE_POP = 47,
BRW_OPCODE_WAIT = 48,
BRW_OPCODE_SEND = 49,
BRW_OPCODE_SENDC = 50,
BRW_OPCODE_MATH = 56,
BRW_OPCODE_ADD = 64,
BRW_OPCODE_MUL = 65,
BRW_OPCODE_AVG = 66,
BRW_OPCODE_FRC = 67,
BRW_OPCODE_RNDU = 68,
BRW_OPCODE_RNDD = 69,
BRW_OPCODE_RNDE = 70,
BRW_OPCODE_RNDZ = 71,
BRW_OPCODE_MAC = 72,
BRW_OPCODE_MACH = 73,
BRW_OPCODE_LZD = 74,
BRW_OPCODE_SAD2 = 80,
BRW_OPCODE_SADA2 = 81,
BRW_OPCODE_DP4 = 84,
BRW_OPCODE_DPH = 85,
BRW_OPCODE_DP3 = 86,
BRW_OPCODE_DP2 = 87,
BRW_OPCODE_DPA2 = 88,
BRW_OPCODE_LINE = 89,
BRW_OPCODE_PLN = 90,
BRW_OPCODE_NOP = 126,
/* These are compiler backend opcodes that get translated into other
* instructions.
*/
FS_OPCODE_FB_WRITE = 128,
FS_OPCODE_RCP,
FS_OPCODE_RSQ,
FS_OPCODE_SQRT,
FS_OPCODE_EXP2,
FS_OPCODE_LOG2,
FS_OPCODE_POW,
FS_OPCODE_SIN,
FS_OPCODE_COS,
FS_OPCODE_DDX,
FS_OPCODE_DDY,
FS_OPCODE_PIXEL_X,
FS_OPCODE_PIXEL_Y,
FS_OPCODE_CINTERP,
FS_OPCODE_LINTERP,
FS_OPCODE_TEX,
FS_OPCODE_TXB,
FS_OPCODE_TXD,
FS_OPCODE_TXL,
FS_OPCODE_DISCARD,
FS_OPCODE_SPILL,
FS_OPCODE_UNSPILL,
FS_OPCODE_PULL_CONSTANT_LOAD,
};
#define BRW_PREDICATE_NONE 0
#define BRW_PREDICATE_NORMAL 1

11
src/mesa/drivers/dri/i965/brw_fs.cpp
View file

@ -522,7 +522,7 @@ fs_visitor::emit_frontfacing_interpolation(ir_variable *ir)
}
fs_inst *
fs_visitor::emit_math(fs_opcodes opcode, fs_reg dst, fs_reg src)
fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src)
{
switch (opcode) {
case FS_OPCODE_RCP:
@ -565,7 +565,7 @@ fs_visitor::emit_math(fs_opcodes opcode, fs_reg dst, fs_reg src)
}
fs_inst *
fs_visitor::emit_math(fs_opcodes opcode, fs_reg dst, fs_reg src0, fs_reg src1)
fs_visitor::emit_math(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
{
int base_mrf = 2;
fs_inst *inst;
@ -1149,6 +1149,9 @@ fs_visitor::propagate_constants()
progress = true;
}
break;
default:
break;
}
}
@ -1200,6 +1203,8 @@ fs_visitor::opt_algebraic()
break;
}
break;
default:
break;
}
}
@ -1267,6 +1272,8 @@ fs_visitor::register_coalesce()
case BRW_OPCODE_ENDIF:
if_depth--;
break;
default:
break;
}
if (loop_depth || if_depth)
continue;

56
src/mesa/drivers/dri/i965/brw_fs.h
View file

@ -25,6 +25,8 @@
*
*/
#include "brw_shader.h"
extern "C" {
#include <sys/types.h>
@ -55,33 +57,6 @@ enum register_file {
BAD_FILE
};
enum fs_opcodes {
FS_OPCODE_FB_WRITE = 256,
FS_OPCODE_RCP,
FS_OPCODE_RSQ,
FS_OPCODE_SQRT,
FS_OPCODE_EXP2,
FS_OPCODE_LOG2,
FS_OPCODE_POW,
FS_OPCODE_SIN,
FS_OPCODE_COS,
FS_OPCODE_DDX,
FS_OPCODE_DDY,
FS_OPCODE_PIXEL_X,
FS_OPCODE_PIXEL_Y,
FS_OPCODE_CINTERP,
FS_OPCODE_LINTERP,
FS_OPCODE_TEX,
FS_OPCODE_TXB,
FS_OPCODE_TXD,
FS_OPCODE_TXL,
FS_OPCODE_DISCARD,
FS_OPCODE_SPILL,
FS_OPCODE_UNSPILL,
FS_OPCODE_PULL_CONSTANT_LOAD,
};
class fs_reg {
public:
/* Callers of this ralloc-based new need not call delete. It's
@ -227,13 +202,13 @@ public:
init();
}
fs_inst(int opcode)
fs_inst(enum opcode opcode)
{
init();
this->opcode = opcode;
}
fs_inst(int opcode, fs_reg dst)
fs_inst(enum opcode opcode, fs_reg dst)
{
init();
this->opcode = opcode;
@ -243,7 +218,7 @@ public:
assert(dst.reg_offset >= 0);
}
fs_inst(int opcode, fs_reg dst, fs_reg src0)
fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0)
{
init();
this->opcode = opcode;
@ -256,7 +231,7 @@ public:
assert(src[0].reg_offset >= 0);
}
fs_inst(int opcode, fs_reg dst, fs_reg src0, fs_reg src1)
fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
{
init();
this->opcode = opcode;
@ -272,7 +247,7 @@ public:
assert(src[1].reg_offset >= 0);
}
fs_inst(int opcode, fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2)
fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2)
{
init();
this->opcode = opcode;
@ -331,7 +306,7 @@ public:
opcode == FS_OPCODE_POW);
}
int opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
fs_reg dst;
fs_reg src[3];
bool saturate;
@ -448,27 +423,28 @@ public:
fs_inst *emit(fs_inst inst);
fs_inst *emit(int opcode)
fs_inst *emit(enum opcode opcode)
{
return emit(fs_inst(opcode));
}
fs_inst *emit(int opcode, fs_reg dst)
fs_inst *emit(enum opcode opcode, fs_reg dst)
{
return emit(fs_inst(opcode, dst));
}
fs_inst *emit(int opcode, fs_reg dst, fs_reg src0)
fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0)
{
return emit(fs_inst(opcode, dst, src0));
}
fs_inst *emit(int opcode, fs_reg dst, fs_reg src0, fs_reg src1)
fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1)
{
return emit(fs_inst(opcode, dst, src0, src1));
}
fs_inst *emit(int opcode, fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2)
fs_inst *emit(enum opcode opcode, fs_reg dst,
fs_reg src0, fs_reg src1, fs_reg src2)
{
return emit(fs_inst(opcode, dst, src0, src1, src2));
}
@ -529,8 +505,8 @@ public:
int sampler);
fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
int sampler);
fs_inst *emit_math(fs_opcodes op, fs_reg dst, fs_reg src0);
fs_inst *emit_math(fs_opcodes op, fs_reg dst, fs_reg src0, fs_reg src1);
fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
bool try_emit_saturate(ir_expression *ir);
void emit_bool_to_cond_code(ir_rvalue *condition);
void emit_if_gen6(ir_if *ir);

6
src/mesa/drivers/dri/i965/brw_fs_emit.cpp
View file

@ -277,6 +277,9 @@ fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
/* There is no sample_d_c message; comparisons are done manually */
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
break;
default:
assert(!"not reached");
break;
}
} else {
switch (inst->opcode) {
@ -317,6 +320,9 @@ fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
assert(inst->mlen == 7 || inst->mlen == 10);
msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
break;
default:
assert(!"not reached");
break;
}
}
assert(msg_type != -1);

20
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
View file

@ -25,23 +25,6 @@
*
*/
extern "C" {
#include <sys/types.h>
#include "main/macros.h"
#include "main/shaderobj.h"
#include "main/uniforms.h"
#include "program/prog_parameter.h"
#include "program/prog_print.h"
#include "program/prog_optimize.h"
#include "program/register_allocate.h"
#include "program/sampler.h"
#include "program/hash_table.h"
#include "brw_context.h"
#include "brw_eu.h"
#include "brw_wm.h"
}
#include "brw_fs.h"
#include "../glsl/glsl_types.h"
#include "../glsl/ir_optimization.h"
@ -359,6 +342,9 @@ fs_visitor::choose_spill_reg(struct ra_graph *g)
if (inst->dst.file == GRF)
no_spill[inst->dst.reg] = true;
break;
default:
break;
}
}

15
src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
View file

@ -25,21 +25,6 @@
*
*/
extern "C" {
#include <sys/types.h>
#include "main/macros.h"
#include "main/shaderobj.h"
#include "main/uniforms.h"
#include "program/prog_optimize.h"
#include "program/register_allocate.h"
#include "program/sampler.h"
#include "program/hash_table.h"
#include "brw_context.h"
#include "brw_eu.h"
#include "brw_wm.h"
}
#include "brw_fs.h"
#include "../glsl/glsl_types.h"
#include "../glsl/ir_optimization.h"

4
src/mesa/drivers/dri/i965/brw_shader.h
View file

@ -21,5 +21,9 @@
* IN THE SOFTWARE.
*/
#include <stdint.h>
#pragma once
int brw_type_for_base_type(const struct glsl_type *type);
uint32_t brw_conditional_for_comparison(unsigned int op);