mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2025-12-20 05:10:11 +01:00
Merge branch 'panvk/pilot' into 'main'
Draft: Very draft! Panvk pilot shaders See merge request mesa/mesa!39009
This commit is contained in:
Faith Ekstrand
commit
600fdfbc09
18 changed files with 697 additions and 166 deletions
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@ -6623,6 +6623,8 @@ bool nir_opt_load_skip_helpers(nir_shader *shader, nir_opt_load_skip_helpers_opt
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void nir_sweep(nir_shader *shader);
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void nir_steal_function(nir_shader *nir, nir_function *f);
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nir_intrinsic_op nir_intrinsic_from_system_value(gl_system_value val);
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gl_system_value nir_system_value_from_intrinsic(nir_intrinsic_op intrin);
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@ -167,7 +167,6 @@ can_move_intrinsic(nir_intrinsic_instr *instr, opt_preamble_ctx *ctx)
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case nir_intrinsic_load_fb_layers_v3d:
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case nir_intrinsic_load_fep_w_v3d:
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case nir_intrinsic_load_tcs_num_patches_amd:
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case nir_intrinsic_load_sample_positions_pan:
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case nir_intrinsic_load_pipeline_stat_query_enabled_amd:
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case nir_intrinsic_load_prim_gen_query_enabled_amd:
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case nir_intrinsic_load_prim_xfb_query_enabled_amd:
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@ -233,6 +232,8 @@ can_move_intrinsic(nir_intrinsic_instr *instr, opt_preamble_ctx *ctx)
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case nir_intrinsic_load_constant_agx:
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case nir_intrinsic_bindless_image_agx:
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case nir_intrinsic_bindless_sampler_agx:
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case nir_intrinsic_load_texel_buf_conv_pan:
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case nir_intrinsic_load_texel_buf_index_address_pan:
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return can_move_srcs(&instr->instr, ctx);
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/* Image/SSBO loads can be moved if they are CAN_REORDER and their
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@ -240,6 +241,7 @@ can_move_intrinsic(nir_intrinsic_instr *instr, opt_preamble_ctx *ctx)
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*/
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case nir_intrinsic_image_load:
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case nir_intrinsic_image_samples_identical:
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case nir_intrinsic_image_texel_address:
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case nir_intrinsic_bindless_image_load:
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case nir_intrinsic_load_global_bounded:
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case nir_intrinsic_load_ssbo:
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@ -813,7 +815,7 @@ nir_opt_preamble(nir_shader *shader, const nir_opt_preamble_options *options,
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if (num_candidates == 0) {
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free(ctx.states);
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return false;
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return nir_no_progress(impl);
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}
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def_state **candidates = malloc(sizeof(*candidates) * num_candidates);
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@ -880,7 +882,7 @@ nir_opt_preamble(nir_shader *shader, const nir_opt_preamble_options *options,
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if (num_candidates == 0) {
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free(ctx.states);
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free(candidates);
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return false;
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return nir_no_progress(impl);
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}
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/* Step 4: Figure out which candidates we're going to replace and assign an
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@ -940,6 +942,12 @@ nir_opt_preamble(nir_shader *shader, const nir_opt_preamble_options *options,
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if (analyze_speculation_for_cf_list(&ctx, &impl->body))
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analyze_reconstructed(&ctx, impl);
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if (!BITSET_TEST_RANGE(ctx.reconstructed_defs, 0, impl->ssa_alloc)) {
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free(ctx.states);
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free(ctx.reconstructed_defs);
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return nir_no_progress(impl);
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}
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/* Step 5: Actually do the replacement. */
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struct hash_table *remap_table =
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_mesa_pointer_hash_table_create(NULL);
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@ -980,11 +988,10 @@ nir_opt_preamble(nir_shader *shader, const nir_opt_preamble_options *options,
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}
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}
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nir_progress(true, impl, nir_metadata_control_flow);
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ralloc_free(remap_table);
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free(ctx.states);
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free(ctx.reconstructed_defs);
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_mesa_set_destroy(ctx.reconstructed_ifs, NULL);
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return true;
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return nir_progress(true, impl, nir_metadata_control_flow);
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}
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@ -185,6 +185,29 @@ sweep_function(nir_shader *nir, nir_function *f)
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sweep_impl(nir, f->impl);
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}
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/** Steals a function from one shader into another.
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*
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* This knows nothing about dependencies so if this function calls other
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* functions, you'll need a more complex pass that uses nir_function_clone()
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* to steal them all.
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*/
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void
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nir_steal_function(nir_shader *nir, nir_function *f)
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{
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#ifndef NDEBUG
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if (f->impl) {
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nir_foreach_block(block, f->impl) {
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nir_foreach_instr(instr, block) {
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assert(instr->type != nir_instr_type_call);
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}
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}
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}
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#endif
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exec_node_remove(&f->node);
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exec_list_push_tail(&nir->functions, &f->node);
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sweep_function(nir, f);
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}
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void
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nir_sweep(nir_shader *nir)
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{
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@ -6504,7 +6504,7 @@ bifrost_lower_texture_late_nir(nir_shader *nir, unsigned gpu_id)
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}
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static int
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compare_u32(const void* a, const void* b, void* _)
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compare_u32(const void* a, const void* b)
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{
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const uint32_t va = (uintptr_t)a;
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const uint32_t vb = (uintptr_t)b;
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@ -6673,7 +6673,7 @@ bi_compile_variant_nir(nir_shader *nir,
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sorted[idx++] = (uintptr_t)entry.data;
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}
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util_qsort_r(sorted, const_amount, sizeof(uint32_t), compare_u32, NULL);
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qsort(sorted, const_amount, sizeof(uint32_t), compare_u32);
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uint32_t max_amount = MIN2(const_amount, ctx->inputs->fau_consts.max_amount);
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uint32_t min_count_for_fau = max_amount > 0 ? sorted[max_amount - 1] : 0;
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ralloc_free(sorted);
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@ -6837,7 +6837,7 @@ bi_compile_variant(nir_shader *nir,
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/* Software invariant: Only a secondary shader can appear at a nonzero
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* offset, to keep the ABI simple. */
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assert((offset == 0) ^ (idvs == BI_IDVS_VARYING));
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assert((offset == 0) ^ (idvs == BI_IDVS_VARYING || idvs == BI_IDVS_PILOT));
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struct pan_stats *stats =
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idvs == BI_IDVS_VARYING ? &info->stats_idvs_varying : &info->stats;
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@ -6874,6 +6874,11 @@ bi_compile_variant(nir_shader *nir,
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info->vs.secondary_offset = offset;
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info->vs.secondary_preload = preload;
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info->vs.secondary_work_reg_count = ctx->info.work_reg_count;
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} else if (idvs == BI_IDVS_PILOT) {
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info->pilot.enable = (binary->size > offset);
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info->pilot.offset = offset;
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info->pilot.preload = preload;
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info->pilot.work_reg_count = ctx->info.work_reg_count;
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} else {
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info->preload = preload;
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info->work_reg_count = ctx->info.work_reg_count;
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@ -6996,6 +7001,26 @@ bifrost_compile_shader_nir(nir_shader *nir,
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info->tls_size = nir->scratch_size;
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nir_shader *pilot = NULL;
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nir_function_impl *entrypoint = nir_shader_get_entrypoint(nir);
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if (entrypoint->preamble) {
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pilot = nir_shader_create(nir, MESA_SHADER_COMPUTE, nir->options);
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pilot->info = nir->info;
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pilot->info.stage = MESA_SHADER_COMPUTE;
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pilot->info.workgroup_size[0] = 1;
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pilot->info.workgroup_size[1] = 1;
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pilot->info.workgroup_size[2] = 1;
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memset(&pilot->info.cs, 0, sizeof(pilot->info.cs));
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nir_function *pilot_main = entrypoint->preamble;
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nir_steal_function(pilot, pilot_main);
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entrypoint->preamble = NULL;
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pilot_main->is_preamble = false;
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pilot_main->is_entrypoint = true;
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}
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pan_nir_collect_varyings(nir, info, PAN_MEDIUMP_VARY_32BIT);
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if (nir->info.stage == MESA_SHADER_VERTEX && info->vs.idvs) {
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@ -7010,6 +7035,9 @@ bifrost_compile_shader_nir(nir_shader *nir,
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bi_compile_variant(nir, inputs, binary, info, BI_IDVS_NONE);
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}
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if (pilot)
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bi_compile_variant(pilot, inputs, binary, info, BI_IDVS_PILOT);
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if (mesa_shader_stage_is_compute(nir->info.stage)) {
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/* Workgroups may be merged if the structure of the workgroup is
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* not software visible. This is true if neither shared memory
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@ -1055,6 +1055,9 @@ enum bi_idvs_mode {
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/* IDVS2 in use. Compiling a deferred shader (v12+) */
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BI_IDVS_ALL = 3,
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/* This is a pilot shader, and not a position or vertex shader */
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BI_IDVS_PILOT = 4,
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};
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#define BI_MAX_REGS 64
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@ -16,6 +16,7 @@ libpanfrost_compiler_files = files(
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'pan_nir_lower_vertex_id.c',
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'pan_nir_lower_writeout.c',
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'pan_nir_lower_xfb.c',
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'pan_nir_opt_pilot.c',
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)
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subdir('bifrost')
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@ -315,6 +315,23 @@ struct pan_shader_info {
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} cs;
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};
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struct {
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/* True if a pilot shader is used */
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bool enable;
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/* If the pilot shader is enabled, number of work registers used by
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* the pilot shader
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*/
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uint16_t work_reg_count;
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/* If the pilot shader is enabled, the pilot shader's offset in the
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* program binary.
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*/
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uint32_t offset;
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/* If the pilot shader is enabled, bit mask of preloaded registers
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* used by the varying shader
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*/
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uint64_t preload;
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} pilot;
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/* Does the shader contains a barrier? or (for fragment shaders) does it
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* require helper invocations, which demand the same ordering guarantees
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* of the hardware? These notions are unified in the hardware, so we
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@ -60,6 +60,26 @@ bool pan_nir_lower_framebuffer(nir_shader *shader,
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unsigned blend_shader_nr_samples,
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bool broken_ld_special);
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struct pan_nir_opt_pilot_params {
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unsigned gpu_id;
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/* Offset in the FAU where the address to the FAU memory lives. This is
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* used for writing FAUs from the pilot shader.
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*/
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uint32_t fau_addr_offset_B;
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/* Offset in the FAU where the pilot data should go */
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uint32_t fau_pilot_data_offset_B;
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/* Amount of space in the FAU available for pilot data */
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uint32_t fau_pilot_data_space_B;
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/* Amount of actual pilot data consumed. This is an output parameter */
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uint32_t pilot_data_size_B;
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};
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bool pan_nir_opt_pilot(nir_shader *nir, struct pan_nir_opt_pilot_params *p);
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uint32_t pan_nir_collect_noperspective_varyings_fs(nir_shader *s);
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/* Specify the mediump lowering behavior for pan_nir_collect_varyings */
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@ -93,20 +93,9 @@ kill_depth_stencil_writes(nir_builder *b, nir_intrinsic_instr *intr,
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return true;
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}
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bool
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pan_nir_lower_zs_store(nir_shader *nir)
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static bool
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lower_zs_store_impl(nir_function_impl *impl)
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{
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bool progress = false;
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if (nir->info.stage != MESA_SHADER_FRAGMENT)
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return false;
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/* Remove all stencil/depth writes if early fragment test is forced. */
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if (nir->info.fs.early_fragment_tests)
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progress |= nir_shader_intrinsics_pass(nir, kill_depth_stencil_writes,
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nir_metadata_control_flow, NULL);
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nir_foreach_function_impl(impl, nir) {
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nir_intrinsic_instr *stores[3] = {NULL};
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nir_intrinsic_instr *last_mask_store = NULL;
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nir_block *mask_block = NULL;
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@ -140,7 +129,7 @@ pan_nir_lower_zs_store(nir_shader *nir)
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}
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if (!writeout && !last_mask_store)
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continue;
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return nir_no_progress(impl);
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nir_block *common_block = mask_block;
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@ -229,8 +218,26 @@ pan_nir_lower_zs_store(nir_shader *nir)
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nir_instr_remove(&stores[i]->instr);
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}
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progress = nir_progress(true, impl, nir_metadata_control_flow);
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return nir_progress(true, impl, nir_metadata_control_flow);
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}
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bool
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pan_nir_lower_zs_store(nir_shader *nir)
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{
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bool progress = false;
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if (nir->info.stage != MESA_SHADER_FRAGMENT) {
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nir_shader_preserve_all_metadata(nir);
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return false;
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}
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/* Remove all stencil/depth writes if early fragment test is forced. */
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if (nir->info.fs.early_fragment_tests)
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progress |= nir_shader_intrinsics_pass(nir, kill_depth_stencil_writes,
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nir_metadata_control_flow, NULL);
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nir_foreach_function_impl(impl, nir)
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progress |= lower_zs_store_impl(impl);
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|
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return progress;
|
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}
|
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|
|
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194
src/panfrost/compiler/pan_nir_opt_pilot.c
Normal file
194
src/panfrost/compiler/pan_nir_opt_pilot.c
Normal file
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|
@ -0,0 +1,194 @@
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/*
|
||||
* Copyright (C) 2025 Collabora, Ltd.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "compiler/nir/nir_builder.h"
|
||||
#include "panfrost/model/pan_model.h"
|
||||
#include "pan_nir.h"
|
||||
|
||||
static void
|
||||
pilot_def_size(nir_def *def, unsigned *size, unsigned *alignment,
|
||||
nir_preamble_class *class)
|
||||
{
|
||||
unsigned bit_size = def->bit_size == 1 ? 32 : def->bit_size;
|
||||
unsigned bits =bit_size * def->num_components;
|
||||
*size = align(bits / 8, 4);
|
||||
*alignment = 4;
|
||||
*class = nir_preamble_class_general;
|
||||
}
|
||||
|
||||
static float
|
||||
pilot_instr_cost(nir_instr *instr, const void *data)
|
||||
{
|
||||
switch (instr->type) {
|
||||
case nir_instr_type_alu: {
|
||||
nir_alu_instr *alu = nir_instr_as_alu(instr);
|
||||
if (alu->def.bit_size == 64 || alu->src[0].src.ssa->bit_size == 64)
|
||||
return 10.0;
|
||||
|
||||
/* Shrug */
|
||||
return 2.0;
|
||||
}
|
||||
|
||||
case nir_instr_type_tex:
|
||||
return 20.0;
|
||||
|
||||
case nir_instr_type_intrinsic:
|
||||
switch (nir_instr_as_intrinsic(instr)->intrinsic) {
|
||||
case nir_intrinsic_load_ubo:
|
||||
case nir_intrinsic_load_global:
|
||||
case nir_intrinsic_load_global_constant:
|
||||
case nir_intrinsic_load_ssbo:
|
||||
return 20.0;
|
||||
default:
|
||||
/* Assume it's a sysval or something */
|
||||
return 0.0;
|
||||
}
|
||||
|
||||
case nir_instr_type_load_const:
|
||||
case nir_instr_type_undef:
|
||||
return 0.0;
|
||||
|
||||
default:
|
||||
return 1.0;
|
||||
}
|
||||
}
|
||||
|
||||
static float
|
||||
pilot_rewrite_cost(nir_def *def, const void *data)
|
||||
{
|
||||
unsigned bit_size = def->bit_size == 1 ? 32 : def->bit_size;
|
||||
unsigned bits = bit_size * def->num_components;
|
||||
unsigned dwords = DIV_ROUND_UP(bits, 32);
|
||||
|
||||
bool needs_mov = false;
|
||||
nir_foreach_use(use, def) {
|
||||
nir_instr *parent_instr = nir_src_parent_instr(use);
|
||||
switch (parent_instr->type) {
|
||||
case nir_instr_type_tex:
|
||||
case nir_instr_type_intrinsic:
|
||||
needs_mov = true;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* It's not a mov but booleans require a conversion */
|
||||
if (def->bit_size == 1)
|
||||
needs_mov = true;
|
||||
|
||||
/* We want rewrites to always cost something or else we'll pull constants
|
||||
* and undefs into the pilot shader.
|
||||
*/
|
||||
return needs_mov ? dwords * 2.0 : 1.0;
|
||||
}
|
||||
|
||||
static bool
|
||||
pilot_avoid_instr(const nir_instr *instr, const void *data)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool
|
||||
lower_pilot_intr(nir_builder *b, nir_intrinsic_instr *intr, void *data)
|
||||
{
|
||||
const struct pan_nir_opt_pilot_params *p = data;
|
||||
|
||||
switch (intr->intrinsic) {
|
||||
case nir_intrinsic_load_subgroup_size: {
|
||||
b->cursor = nir_before_instr(&intr->instr);
|
||||
unsigned sg_size = pan_subgroup_size(pan_arch(p->gpu_id));
|
||||
nir_def_replace(&intr->def, nir_imm_int(b, sg_size));
|
||||
return true;
|
||||
}
|
||||
|
||||
case nir_intrinsic_load_preamble: {
|
||||
b->cursor = nir_before_instr(&intr->instr);
|
||||
|
||||
uint32_t offset = p->fau_pilot_data_offset_B + nir_intrinsic_base(intr);
|
||||
assert(offset % 4 == 0);
|
||||
|
||||
unsigned bit_size = intr->def.bit_size == 1 ? 32 : intr->def.bit_size;
|
||||
unsigned bits = bit_size * intr->def.num_components;
|
||||
nir_def *val = nir_load_push_constant(b,
|
||||
DIV_ROUND_UP(bits, 32), 32, nir_imm_int(b, offset));
|
||||
|
||||
val = nir_bitcast_vector(b, val, bit_size);
|
||||
val = nir_trim_vector(b, val, intr->def.num_components);
|
||||
|
||||
if (intr->def.bit_size == 1)
|
||||
val = nir_b2b1(b, val);
|
||||
|
||||
nir_def_replace(&intr->def, val);
|
||||
return true;
|
||||
}
|
||||
|
||||
case nir_intrinsic_store_preamble: {
|
||||
b->cursor = nir_before_instr(&intr->instr);
|
||||
|
||||
nir_def *val = intr->src[0].ssa;
|
||||
if (val->bit_size == 1)
|
||||
val = nir_b2b32(b, val);
|
||||
|
||||
nir_def *push_const_buf = nir_load_push_constant(
|
||||
b, 1, 64, nir_imm_int(b, p->fau_addr_offset_B));
|
||||
|
||||
uint32_t offset = p->fau_pilot_data_offset_B + nir_intrinsic_base(intr);
|
||||
|
||||
nir_store_global(b, val, nir_iadd_imm(b, push_const_buf, offset),
|
||||
.align_mul = 4);
|
||||
|
||||
nir_instr_remove(&intr->instr);
|
||||
return true;
|
||||
}
|
||||
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
bool
|
||||
pan_nir_opt_pilot(nir_shader *nir, struct pan_nir_opt_pilot_params *p)
|
||||
{
|
||||
bool progress = false;
|
||||
|
||||
const nir_opt_preamble_options preamble_opts = {
|
||||
.subgroup_size_uniform = true,
|
||||
.def_size = pilot_def_size,
|
||||
.preamble_storage_size = {
|
||||
[nir_preamble_class_general] = p->fau_pilot_data_space_B,
|
||||
},
|
||||
.instr_cost_cb = pilot_instr_cost,
|
||||
.rewrite_cost_cb = pilot_rewrite_cost,
|
||||
.avoid_instr_cb = pilot_avoid_instr,
|
||||
};
|
||||
NIR_PASS(progress, nir, nir_opt_preamble, &preamble_opts,
|
||||
&p->pilot_data_size_B);
|
||||
if (!progress)
|
||||
return false;
|
||||
|
||||
NIR_PASS(progress, nir, nir_shader_intrinsics_pass, lower_pilot_intr,
|
||||
nir_metadata_control_flow, p);
|
||||
|
||||
return progress;
|
||||
}
|
||||
|
|
@ -172,9 +172,11 @@ cmd_dispatch(struct panvk_cmd_buffer *cmdbuf, struct panvk_dispatch_info *info)
|
|||
if (result != VK_SUCCESS)
|
||||
return;
|
||||
|
||||
if (compute_state_dirty(cmdbuf, PUSH_UNIFORMS)) {
|
||||
result = panvk_per_arch(cmd_prepare_push_uniforms)(cmdbuf, cs, 1);
|
||||
if (result != VK_SUCCESS)
|
||||
return;
|
||||
}
|
||||
|
||||
if (compute_state_dirty(cmdbuf, CS) ||
|
||||
compute_state_dirty(cmdbuf, DESC_STATE)) {
|
||||
|
|
|
|||
|
|
@ -452,6 +452,89 @@ prepare_fs_driver_set(struct panvk_cmd_buffer *cmdbuf)
|
|||
return VK_SUCCESS;
|
||||
}
|
||||
|
||||
static void
|
||||
launch_pilot(struct panvk_cmd_buffer *cmdbuf,
|
||||
const struct panvk_shader_variant *s,
|
||||
struct panvk_shader_desc_state *desc_state,
|
||||
uint64_t push_uniforms)
|
||||
{
|
||||
if (!s->info.pilot.enable)
|
||||
return;
|
||||
|
||||
const struct pan_compute_dim job_size = { 1, 1, 1 };
|
||||
|
||||
struct cs_builder *b = panvk_get_cs_builder(cmdbuf, PANVK_SUBQUEUE_COMPUTE);
|
||||
cs_update_compute_ctx(b) {
|
||||
cs_move64_to(b, cs_sr_reg64(b, COMPUTE, SRT_2),
|
||||
desc_state->res_table);
|
||||
|
||||
uint64_t fau_ptr = push_uniforms | ((uint64_t)s->fau.total_count << 56);
|
||||
cs_move64_to(b, cs_sr_reg64(b, COMPUTE, FAU_2), fau_ptr);
|
||||
|
||||
cs_move64_to(b, cs_sr_reg64(b, COMPUTE, SPD_2),
|
||||
panvk_priv_mem_dev_addr(s->pilot_spd));
|
||||
|
||||
/* TSD_2 is set in update_tls() */
|
||||
|
||||
struct mali_compute_size_workgroup_packed wg_size;
|
||||
pan_pack(&wg_size, COMPUTE_SIZE_WORKGROUP, cfg) {
|
||||
cfg.workgroup_size_x = 1;
|
||||
cfg.workgroup_size_y = 1;
|
||||
cfg.workgroup_size_z = 1;
|
||||
cfg.allow_merging_workgroups = true;
|
||||
}
|
||||
cs_move32_to(b, cs_sr_reg32(b, COMPUTE, WG_SIZE), wg_size.opaque[0]);
|
||||
|
||||
cs_move32_to(b, cs_sr_reg32(b, COMPUTE, JOB_OFFSET_X), 0);
|
||||
cs_move32_to(b, cs_sr_reg32(b, COMPUTE, JOB_OFFSET_Y), 0);
|
||||
cs_move32_to(b, cs_sr_reg32(b, COMPUTE, JOB_OFFSET_Z), 0);
|
||||
cs_move32_to(b, cs_sr_reg32(b, COMPUTE, JOB_SIZE_X), job_size.x);
|
||||
cs_move32_to(b, cs_sr_reg32(b, COMPUTE, JOB_SIZE_Y), job_size.y);
|
||||
cs_move32_to(b, cs_sr_reg32(b, COMPUTE, JOB_SIZE_Z), job_size.z);
|
||||
}
|
||||
|
||||
const struct cs_tracing_ctx *tracing_ctx =
|
||||
&cmdbuf->state.cs[PANVK_SUBQUEUE_COMPUTE].tracing;
|
||||
cs_trace_run_compute(b, tracing_ctx, cs_scratch_reg_tuple(b, 0, 4),
|
||||
1, MALI_TASK_AXIS_X, cs_shader_res_sel(2, 2, 2, 2));
|
||||
|
||||
#if PAN_ARCH >= 11
|
||||
struct cs_index sync_addr = cs_scratch_reg64(b, 0);
|
||||
struct cs_index add_val = cs_scratch_reg64(b, 2);
|
||||
|
||||
cs_load64_to(b, sync_addr, cs_subqueue_ctx_reg(b),
|
||||
offsetof(struct panvk_cs_subqueue_context, syncobjs));
|
||||
|
||||
cs_add64(b, sync_addr, sync_addr,
|
||||
PANVK_SUBQUEUE_COMPUTE * sizeof(struct panvk_cs_sync64));
|
||||
cs_move64_to(b, add_val, 1);
|
||||
panvk_instr_sync64_add(cmdbuf, PANVK_SUBQUEUE_COMPUTE, true,
|
||||
MALI_CS_SYNC_SCOPE_CSG, add_val, sync_addr,
|
||||
cs_defer_indirect());
|
||||
#else
|
||||
struct cs_index sync_addr = cs_scratch_reg64(b, 0);
|
||||
struct cs_index iter_sb = cs_scratch_reg32(b, 2);
|
||||
struct cs_index cmp_scratch = cs_scratch_reg32(b, 3);
|
||||
struct cs_index add_val = cs_scratch_reg64(b, 4);
|
||||
|
||||
cs_load_to(b, cs_scratch_reg_tuple(b, 0, 3), cs_subqueue_ctx_reg(b),
|
||||
BITFIELD_MASK(3),
|
||||
offsetof(struct panvk_cs_subqueue_context, syncobjs));
|
||||
|
||||
cs_add64(b, sync_addr, sync_addr,
|
||||
PANVK_SUBQUEUE_COMPUTE * sizeof(struct panvk_cs_sync64));
|
||||
cs_move64_to(b, add_val, 1);
|
||||
|
||||
cs_match_iter_sb(b, x, iter_sb, cmp_scratch) {
|
||||
panvk_instr_sync64_add(cmdbuf, PANVK_SUBQUEUE_COMPUTE, true,
|
||||
MALI_CS_SYNC_SCOPE_CSG, add_val, sync_addr,
|
||||
cs_defer(SB_WAIT_ITER(x), SB_ID(DEFERRED_SYNC)));
|
||||
}
|
||||
#endif
|
||||
|
||||
++cmdbuf->state.cs[PANVK_SUBQUEUE_COMPUTE].relative_sync_point;
|
||||
}
|
||||
|
||||
static bool
|
||||
has_depth_att(struct panvk_cmd_buffer *cmdbuf)
|
||||
{
|
||||
|
|
@ -596,6 +679,8 @@ update_tls(struct panvk_cmd_buffer *cmdbuf)
|
|||
panvk_shader_only_variant(cmdbuf->state.gfx.fs.shader);
|
||||
struct cs_builder *b =
|
||||
panvk_get_cs_builder(cmdbuf, PANVK_SUBQUEUE_VERTEX_TILER);
|
||||
struct cs_builder *cs_b =
|
||||
panvk_get_cs_builder(cmdbuf, PANVK_SUBQUEUE_COMPUTE);
|
||||
|
||||
if (!cmdbuf->state.gfx.tsd) {
|
||||
if (!state->desc.gpu) {
|
||||
|
|
@ -616,6 +701,10 @@ update_tls(struct panvk_cmd_buffer *cmdbuf)
|
|||
cs_move64_to(b, cs_sr_reg64(b, IDVS, TSD_0), state->desc.gpu);
|
||||
#endif
|
||||
}
|
||||
|
||||
cs_update_compute_ctx(cs_b) {
|
||||
cs_move64_to(cs_b, cs_sr_reg64(b, COMPUTE, TSD_2), state->desc.gpu);
|
||||
}
|
||||
}
|
||||
|
||||
state->info.tls.size =
|
||||
|
|
@ -1764,7 +1853,10 @@ prepare_push_uniforms(struct panvk_cmd_buffer *cmdbuf,
|
|||
}
|
||||
}
|
||||
|
||||
if (fs_user_dirty(cmdbuf) || gfx_state_dirty(cmdbuf, FS_PUSH_UNIFORMS)) {
|
||||
bool fs_pilot = fs && fs->info.pilot.enable;
|
||||
if (fs_user_dirty(cmdbuf) ||
|
||||
(fs_pilot && gfx_state_dirty(cmdbuf, DESC_STATE)) ||
|
||||
gfx_state_dirty(cmdbuf, FS_PUSH_UNIFORMS)) {
|
||||
uint64_t fau_ptr = 0;
|
||||
|
||||
if (fs) {
|
||||
|
|
@ -1772,6 +1864,10 @@ prepare_push_uniforms(struct panvk_cmd_buffer *cmdbuf,
|
|||
if (result != VK_SUCCESS)
|
||||
return result;
|
||||
|
||||
if (fs->info.pilot.enable)
|
||||
launch_pilot(cmdbuf, fs, &cmdbuf->state.gfx.fs.desc,
|
||||
cmdbuf->state.gfx.fs.push_uniforms);
|
||||
|
||||
fau_ptr = cmdbuf->state.gfx.fs.push_uniforms |
|
||||
((uint64_t)fs->fau.total_count << 56);
|
||||
}
|
||||
|
|
@ -2310,10 +2406,6 @@ prepare_draw(struct panvk_cmd_buffer *cmdbuf, struct panvk_draw_info *draw)
|
|||
|
||||
panvk_per_arch(cmd_prepare_draw_sysvals)(cmdbuf, draw);
|
||||
|
||||
result = prepare_push_uniforms(cmdbuf, draw);
|
||||
if (result != VK_SUCCESS)
|
||||
return result;
|
||||
|
||||
result = prepare_vs(cmdbuf, draw);
|
||||
if (result != VK_SUCCESS)
|
||||
return result;
|
||||
|
|
@ -2322,6 +2414,10 @@ prepare_draw(struct panvk_cmd_buffer *cmdbuf, struct panvk_draw_info *draw)
|
|||
if (result != VK_SUCCESS)
|
||||
return result;
|
||||
|
||||
result = prepare_push_uniforms(cmdbuf, draw);
|
||||
if (result != VK_SUCCESS)
|
||||
return result;
|
||||
|
||||
/* Assumes 16 byte slots. We could do better. */
|
||||
uint32_t varying_size = get_varying_slots(cmdbuf) * 16;
|
||||
|
||||
|
|
@ -3069,6 +3165,17 @@ issue_fragment_jobs(struct panvk_cmd_buffer *cmdbuf)
|
|||
struct cs_builder *b = panvk_get_cs_builder(cmdbuf, PANVK_SUBQUEUE_FRAGMENT);
|
||||
bool has_oq_chain = cmdbuf->state.gfx.render.oq.chain != 0;
|
||||
|
||||
/* Wait on any pilot shaders */
|
||||
const struct panvk_cs_deps deps = {
|
||||
.src[PANVK_SUBQUEUE_COMPUTE] = {
|
||||
.wait_sb_mask = dev->csf.sb.all_iters_mask,
|
||||
},
|
||||
.dst[PANVK_SUBQUEUE_FRAGMENT] = {
|
||||
.wait_subqueue_mask = BITFIELD_BIT(PANVK_SUBQUEUE_COMPUTE),
|
||||
},
|
||||
};
|
||||
panvk_per_arch(emit_barrier)(cmdbuf, deps);
|
||||
|
||||
/* Now initialize the fragment bits. */
|
||||
cs_update_frag_ctx(b) {
|
||||
cs_move32_to(b, cs_sr_reg32(b, FRAGMENT, BBOX_MIN),
|
||||
|
|
|
|||
|
|
@ -103,9 +103,11 @@ cmd_dispatch(struct panvk_cmd_buffer *cmdbuf, struct panvk_dispatch_info *info)
|
|||
|
||||
panvk_per_arch(cmd_prepare_dispatch_sysvals)(cmdbuf, info);
|
||||
|
||||
if (compute_state_dirty(cmdbuf, PUSH_UNIFORMS)) {
|
||||
result = panvk_per_arch(cmd_prepare_push_uniforms)(cmdbuf, cs, 1);
|
||||
if (result != VK_SUCCESS)
|
||||
return;
|
||||
}
|
||||
|
||||
struct pan_ptr copy_desc_job = {0};
|
||||
|
||||
|
|
|
|||
|
|
@ -1471,12 +1471,14 @@ panvk_cmd_draw(struct panvk_cmd_buffer *cmdbuf, struct panvk_draw_data *draw)
|
|||
gfx_state_set_dirty(cmdbuf, FS_PUSH_UNIFORMS);
|
||||
}
|
||||
|
||||
if (compute_state_dirty(cmdbuf, PUSH_UNIFORMS)) {
|
||||
result = panvk_per_arch(cmd_prepare_push_uniforms)(
|
||||
cmdbuf, vs, 1);
|
||||
if (result != VK_SUCCESS)
|
||||
return;
|
||||
}
|
||||
|
||||
if (fs) {
|
||||
if (fs && compute_state_dirty(cmdbuf, PUSH_UNIFORMS)) {
|
||||
result = panvk_per_arch(cmd_prepare_push_uniforms)(
|
||||
cmdbuf, fs, 1);
|
||||
if (result != VK_SUCCESS)
|
||||
|
|
@ -1633,12 +1635,14 @@ panvk_cmd_draw_indirect(struct panvk_cmd_buffer *cmdbuf,
|
|||
gfx_state_set_dirty(cmdbuf, FS_PUSH_UNIFORMS);
|
||||
}
|
||||
|
||||
if (compute_state_dirty(cmdbuf, PUSH_UNIFORMS)) {
|
||||
result = panvk_per_arch(cmd_prepare_push_uniforms)(
|
||||
cmdbuf, vs, 1);
|
||||
if (result != VK_SUCCESS)
|
||||
return;
|
||||
}
|
||||
|
||||
if (fs) {
|
||||
if (fs && compute_state_dirty(cmdbuf, PUSH_UNIFORMS)) {
|
||||
result = panvk_per_arch(cmd_prepare_push_uniforms)(
|
||||
cmdbuf, fs, 1);
|
||||
if (result != VK_SUCCESS)
|
||||
|
|
|
|||
|
|
@ -348,6 +348,8 @@ struct panvk_shader_fau_info {
|
|||
BITSET_DECLARE(used_sysvals, MAX_SYSVAL_FAUS);
|
||||
BITSET_DECLARE(used_push_consts, MAX_PUSH_CONST_FAUS);
|
||||
uint32_t sysval_count;
|
||||
uint32_t push_count;
|
||||
uint32_t pilot_count;
|
||||
uint32_t total_count;
|
||||
};
|
||||
|
||||
|
|
@ -416,6 +418,7 @@ struct panvk_shader_variant {
|
|||
#endif
|
||||
} spds;
|
||||
};
|
||||
struct panvk_priv_mem pilot_spd;
|
||||
#endif
|
||||
|
||||
const char *nir_str;
|
||||
|
|
|
|||
|
|
@ -17,18 +17,12 @@ panvk_per_arch(cmd_prepare_push_uniforms)(
|
|||
|
||||
switch (shader->info.stage) {
|
||||
case MESA_SHADER_COMPUTE:
|
||||
if (!compute_state_dirty(cmdbuf, PUSH_UNIFORMS))
|
||||
return VK_SUCCESS;
|
||||
push_ptr = &cmdbuf->state.compute.push_uniforms;
|
||||
break;
|
||||
case MESA_SHADER_VERTEX:
|
||||
if (!gfx_state_dirty(cmdbuf, VS_PUSH_UNIFORMS))
|
||||
return VK_SUCCESS;
|
||||
push_ptr = &cmdbuf->state.gfx.vs.push_uniforms;
|
||||
break;
|
||||
case MESA_SHADER_FRAGMENT:
|
||||
if (!gfx_state_dirty(cmdbuf, FS_PUSH_UNIFORMS))
|
||||
return VK_SUCCESS;
|
||||
push_ptr = &cmdbuf->state.gfx.fs.push_uniforms;
|
||||
break;
|
||||
default:
|
||||
|
|
@ -78,6 +72,9 @@ panvk_per_arch(cmd_prepare_push_uniforms)(
|
|||
BITSET_FOREACH_SET(w, shader->fau.used_push_consts, MAX_PUSH_CONST_FAUS)
|
||||
faus[fau++] = push_consts[w];
|
||||
|
||||
/* These are populated by the pilot shader */
|
||||
fau += shader->fau.pilot_count;
|
||||
|
||||
for (uint32_t i = 0; i < shader->info.fau_consts_count; i += 2) {
|
||||
faus[fau++] = (uint64_t)shader->info.fau_consts[i + 1] << 32 |
|
||||
shader->info.fau_consts[i];
|
||||
|
|
|
|||
|
|
@ -569,7 +569,7 @@ load_resource_deref_desc(nir_builder *b, nir_deref_instr *deref,
|
|||
b, num_components, bit_size,
|
||||
nir_imm_int(b, pan_res_handle(VALHALL_RESOURCE_TABLE_IDX, set + 1)),
|
||||
set_offset, .range = ~0u, .align_mul = PANVK_DESCRIPTOR_SIZE,
|
||||
.align_offset = desc_offset);
|
||||
.align_offset = desc_offset, .access = ACCESS_CAN_SPECULATE);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
@ -1162,6 +1162,9 @@ static bool
|
|||
collect_tex_desc_access(nir_builder *b, nir_tex_instr *tex,
|
||||
struct lower_desc_ctx *ctx)
|
||||
{
|
||||
/* We'll also set can_speculate here. */
|
||||
tex->can_speculate = true;
|
||||
|
||||
bool recorded = false;
|
||||
uint32_t plane = 0;
|
||||
int sampler_src_idx =
|
||||
|
|
@ -1184,6 +1187,9 @@ collect_tex_desc_access(nir_builder *b, nir_tex_instr *tex,
|
|||
struct panvk_subdesc_info subdesc =
|
||||
get_sampler_subdesc_info(binding_layout->type, plane);
|
||||
|
||||
if (binding_layout->flags & VK_DESCRIPTOR_BINDING_PARTIALLY_BOUND_BIT)
|
||||
tex->can_speculate = false;
|
||||
|
||||
record_binding(ctx, set, binding, subdesc, max_idx);
|
||||
recorded = true;
|
||||
}
|
||||
|
|
@ -1203,6 +1209,9 @@ collect_tex_desc_access(nir_builder *b, nir_tex_instr *tex,
|
|||
struct panvk_subdesc_info subdesc =
|
||||
get_tex_subdesc_info(binding_layout->type, plane);
|
||||
|
||||
if (binding_layout->flags & VK_DESCRIPTOR_BINDING_PARTIALLY_BOUND_BIT)
|
||||
tex->can_speculate = false;
|
||||
|
||||
record_binding(ctx, set, binding, subdesc, max_idx);
|
||||
recorded = true;
|
||||
}
|
||||
|
|
@ -1210,11 +1219,66 @@ collect_tex_desc_access(nir_builder *b, nir_tex_instr *tex,
|
|||
return recorded;
|
||||
}
|
||||
|
||||
static bool
|
||||
mark_load_can_speculate(nir_intrinsic_instr *load,
|
||||
const struct lower_desc_ctx *ctx)
|
||||
{
|
||||
assert(load->intrinsic == nir_intrinsic_load_deref);
|
||||
|
||||
/* If it's already marked CAN_SPECULATE, there's nothing to do */
|
||||
enum gl_access_qualifier access = nir_intrinsic_access(load);
|
||||
if (access & ACCESS_CAN_SPECULATE)
|
||||
return false;
|
||||
|
||||
nir_deref_instr *deref = nir_src_as_deref(load->src[0]);
|
||||
if (!nir_deref_mode_is_one_of(deref, nir_var_mem_ubo | nir_var_mem_ssbo))
|
||||
return false;
|
||||
|
||||
if (nir_deref_mode_is(deref, nir_var_mem_ssbo) &&
|
||||
((access & ACCESS_VOLATILE) || !(access & ACCESS_CAN_REORDER)))
|
||||
return false;
|
||||
|
||||
while (true) {
|
||||
nir_deref_instr *parent = nir_deref_instr_parent(deref);
|
||||
if (parent == NULL)
|
||||
break;
|
||||
deref = parent;
|
||||
}
|
||||
assert(deref->deref_type == nir_deref_type_cast);
|
||||
|
||||
nir_intrinsic_instr *desc_load = nir_src_as_intrinsic(deref->parent);
|
||||
if (desc_load == NULL ||
|
||||
desc_load->intrinsic != nir_intrinsic_load_vulkan_descriptor)
|
||||
return false;
|
||||
|
||||
nir_intrinsic_instr *desc_index = nir_src_as_intrinsic(desc_load->src[0]);
|
||||
if (desc_index == NULL ||
|
||||
desc_index->intrinsic != nir_intrinsic_vulkan_resource_index)
|
||||
return false;
|
||||
|
||||
unsigned set = nir_intrinsic_desc_set(desc_index);
|
||||
unsigned binding = nir_intrinsic_binding(desc_index);
|
||||
const struct panvk_descriptor_set_layout *set_layout =
|
||||
get_set_layout(set, ctx);
|
||||
const struct panvk_descriptor_set_binding_layout *bind_layout =
|
||||
&set_layout->bindings[binding];
|
||||
|
||||
if (bind_layout->flags & VK_DESCRIPTOR_BINDING_PARTIALLY_BOUND_BIT)
|
||||
return false;
|
||||
|
||||
access |= ACCESS_CAN_SPECULATE;
|
||||
nir_intrinsic_set_access(load, access);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool
|
||||
collect_intr_desc_access(nir_builder *b, nir_intrinsic_instr *intrin,
|
||||
struct lower_desc_ctx *ctx)
|
||||
{
|
||||
switch (intrin->intrinsic) {
|
||||
case nir_intrinsic_load_deref:
|
||||
return mark_load_can_speculate(intrin, ctx);
|
||||
|
||||
case nir_intrinsic_vulkan_resource_index: {
|
||||
unsigned set, binding;
|
||||
|
||||
|
|
@ -1338,6 +1402,9 @@ panvk_per_arch(nir_lower_descriptors)(
|
|||
for (uint32_t i = 0; i < set_layout_count; i++)
|
||||
ctx.set_layouts[i] = to_panvk_descriptor_set_layout(set_layouts[i]);
|
||||
|
||||
/* Collect descriptor access. This also marks texture and UBO/SSBO loads
|
||||
* as can_speculate based on descriptor binding flags.
|
||||
*/
|
||||
NIR_PASS(progress, nir, nir_shader_instructions_pass,
|
||||
collect_instr_desc_access, nir_metadata_all, &ctx);
|
||||
if (!progress)
|
||||
|
|
|
|||
|
|
@ -65,6 +65,12 @@
|
|||
#include "vk_shader.h"
|
||||
#include "vk_util.h"
|
||||
|
||||
static inline bool
|
||||
panvk_wants_pilot_shader(mesa_shader_stage stage, unsigned arch)
|
||||
{
|
||||
return arch >= 9 && stage == MESA_SHADER_FRAGMENT;
|
||||
}
|
||||
|
||||
#define FAU_WORD_COUNT 64
|
||||
|
||||
struct panvk_lower_sysvals_context {
|
||||
|
|
@ -700,6 +706,9 @@ lower_load_push_consts(nir_shader *nir, struct panvk_shader_variant *shader)
|
|||
shader_use_sysval(shader, graphics, blend.constants);
|
||||
}
|
||||
|
||||
if (panvk_wants_pilot_shader(nir->info.stage, PAN_ARCH))
|
||||
shader_use_sysval(shader, common, push_uniforms);
|
||||
|
||||
progress = false;
|
||||
NIR_PASS(progress, nir, nir_shader_intrinsics_pass, collect_push_constant,
|
||||
nir_metadata_all, shader);
|
||||
|
|
@ -717,8 +726,8 @@ lower_load_push_consts(nir_shader *nir, struct panvk_shader_variant *shader)
|
|||
/* 32 FAUs (256 bytes) are reserved for API push constants */
|
||||
assert(shader->fau.sysval_count <= FAU_WORD_COUNT - 32 &&
|
||||
"too many sysval FAUs");
|
||||
shader->fau.total_count =
|
||||
shader->fau.sysval_count + BITSET_COUNT(shader->fau.used_push_consts);
|
||||
shader->fau.push_count = BITSET_COUNT(shader->fau.used_push_consts);
|
||||
shader->fau.total_count = shader->fau.sysval_count + shader->fau.push_count;
|
||||
assert(shader->fau.total_count <= FAU_WORD_COUNT &&
|
||||
"asking for more FAUs than the hardware has to offer");
|
||||
|
||||
|
|
@ -925,6 +934,26 @@ panvk_compile_nir(struct panvk_device *dev, nir_shader *nir,
|
|||
|
||||
lower_load_push_consts(nir, shader);
|
||||
|
||||
if (panvk_wants_pilot_shader(nir->info.stage, PAN_ARCH)) {
|
||||
/* Our pilots will be more efficient if we optimize first. */
|
||||
pan_optimize_nir(nir, input.gpu_id);
|
||||
|
||||
struct pan_nir_opt_pilot_params pilot = {
|
||||
.gpu_id = input.gpu_id,
|
||||
.fau_addr_offset_B = shader_remapped_sysval_offset(
|
||||
shader, sysval_offset(common, push_uniforms)),
|
||||
.fau_pilot_data_offset_B =
|
||||
FAU_WORD_SIZE * shader->fau.total_count,
|
||||
.fau_pilot_data_space_B =
|
||||
FAU_WORD_SIZE * (FAU_WORD_COUNT - shader->fau.total_count),
|
||||
};
|
||||
pan_nir_opt_pilot(nir, &pilot);
|
||||
|
||||
shader->fau.pilot_count =
|
||||
DIV_ROUND_UP(pilot.pilot_data_size_B, FAU_WORD_SIZE);
|
||||
shader->fau.total_count += shader->fau.pilot_count;
|
||||
}
|
||||
|
||||
/* Allow the remaining FAU space to be filled with constants. */
|
||||
input.fau_consts.max_amount =
|
||||
2 * (FAU_WORD_COUNT - shader->fau.total_count);
|
||||
|
|
@ -1208,6 +1237,23 @@ panvk_shader_upload(struct panvk_device *dev,
|
|||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
if (shader->info.pilot.enable) {
|
||||
shader->pilot_spd =
|
||||
panvk_pool_alloc_desc(&dev->mempools.rw, SHADER_PROGRAM);
|
||||
if (!panvk_priv_mem_check_alloc(shader->pilot_spd))
|
||||
return panvk_error(dev, VK_ERROR_OUT_OF_DEVICE_MEMORY);
|
||||
|
||||
panvk_priv_mem_write_desc(shader->pilot_spd, 0, SHADER_PROGRAM, cfg) {
|
||||
cfg.stage = MALI_SHADER_STAGE_COMPUTE,
|
||||
cfg.register_allocation =
|
||||
pan_register_allocation(shader->info.pilot.work_reg_count);
|
||||
cfg.binary = panvk_shader_variant_get_dev_addr(shader) +
|
||||
shader->info.pilot.offset;
|
||||
cfg.preload.r48_r63 = (shader->info.pilot.preload >> 48);
|
||||
cfg.flush_to_zero_mode = shader_ftz_mode(shader);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
return VK_SUCCESS;
|
||||
|
|
@ -1237,6 +1283,7 @@ panvk_shader_variant_destroy(struct panvk_shader_variant *shader)
|
|||
panvk_pool_free_mem(&shader->spds.pos_triangles);
|
||||
#endif
|
||||
}
|
||||
panvk_pool_free_mem(&shader->pilot_spd);
|
||||
#endif
|
||||
|
||||
if (shader->own_bin)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue